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Add tileable RR Graph #3134
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b6371d2
[vpr][rr_graph] add tileable rr graph dir
amin1377 77781b4
[vpr][rr_graph] move tileable rr graph dir uner rr_graph_generation
amin1377 cf95e2c
[vpr][route] update rr_graph generation with tileable rr graph
amin1377 431923c
[vpr][util] add is_inter_cluster_node for vib arch
amin1377 d62fb79
[vpr][route] update router lookahead with tileable rr graph
amin1377 02a56e9
[vpr][blif] use regex to find param val
amin1377 204a794
[vpr][base] update with tileable rr graph
amin1377 7edf56d
[vpr][route] remove unused param
amin1377 f5e8061
[lib][arch] add vib processing
amin1377 14064c7
[lib][arch] add vib_inf
amin1377 49b04b0
[libs][rr_graph] update lib rr graph with tileable
amin1377 c6df91a
[libs][rr graph][io] update read/write rr graph functions with tileab…
amin1377 bf19150
[libs][rr graph][io] update rr_grpah utils with tileable info
amin1377 3970db7
[lib][rr_graph] add vtr tokenizer
amin1377 797b488
[lib][util] update capnp and util with open fpga
amin1377 cf2dbc8
add openfpga doc
amin1377 0e03dc7
[vpr][base] add vib grid
amin1377 f8fae78
add VIB doc
amin1377 5462ccd
[vpr][route] fix alloc_and_load_rr_switch_inf definition
amin1377 7cdf5bf
make format
amin1377 5ad8303
[vtr_flow][test] add openfpga arch
amin1377 c79ab8f
[CI] add openfpga tests
amin1377 8eccbcc
fix formatting
amin1377 0cc6f10
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 5a492c8
[doc][arch] add tileable doc
amin1377 1fd866e
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 5580c86
[libs][arch] add function declarations
amin1377 a27f6ba
[rr_graph] change MEDIUM node type name and related function to MUX
amin1377 8625ff0
[libs][arch] add process_bend
amin1377 57c1919
make format
amin1377 29c9677
[doc] fix a typo in .bib file
amin1377 b6fdda3
[vpr] remove redundant version of is_inter_cluster_node
amin1377 2b68252
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 65102b9
[doc][arch] move openfpga doc to the end of the file
amin1377 757e2f7
[doc][arch] add figures related to direct connection
amin1377 2b2fbb4
[doc][arch] add doc related to tileable direct interconnect
amin1377 6e5070c
[arch] change isbend to is_bend
amin1377 43ac8b4
[tileable_rr_graph] fix sub_fs formatting
amin1377 5436025
[rr_graph] comment tileable rr_graph function under rr_graph_builder.h
amin1377 09c90f2
[libs][rr_graph] mode bend_start/end out of t_rr_node_data
amin1377 e3df5b5
[base] fix function names formatting
amin1377 e08cd8c
make format
amin1377 9c87418
[libs][matrix] check for size before filling the matrix
amin1377 0df7730
[libs][rr_graph] fix node_bend_start/end size
amin1377 837278b
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 7c6a979
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 ca95008
[libs][arch] fix c-style code in read_xml_arch_file
amin1377 bb9a338
[lib][arch] fix process_vib_block_type_locs style
amin1377 af27706
[lib][arch] pass set funcitons params by reference
amin1377 4194e81
Apply code review comment
amin1377 561a0d5
make format
amin1377 07d4bac
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 4e38274
fix a typo
amin1377 f324567
[libs][arch] fix clang-17 warning
amin1377 1f929ea
[vpr][route][tileable] replace VTR_LOG to VTR_LOG_DEBUG & fix c-style…
amin1377 bc7ffcd
[libs][vtrutil] fix string_view error
amin1377 9cf3775
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 5f1939c
[vpr][utils] move StringToken under vtr util
amin1377 bd62d9f
[vpr][base] remove unnecessary auto
amin1377 1d1318d
[vpr] apply code format rules to tileable RR Graph files
amin1377 4c60c9d
[libs][arch] move vib arch functions to a separate file
amin1377 70836c5
make format
amin1377 2b101ef
[doc] fix grammatical issues
amin1377 edd3617
[libs][arch] fix sb_type sb_sub_type name
amin1377 205514f
[libs][arch] fix formatting
amin1377 28fc161
[libs][arch] fix code formatting
amin1377 59f1c86
[libs][arch] replace e_parallel_axis_vib with e_parallel_axis
amin1377 55c3f2f
[libs][rr_graph] fix tileable rr graph code format
amin1377 d168828
[libs][util] extern out_file_prefix
amin1377 34d0e65
[vpr][route] add e_parallel_axis identifier for all members
amin1377 7beed40
[libs][arch] add a method to parse tileable arch tags
amin1377 211c270
[libs][rr_graph] add comment for tileable rr graph
amin1377 4cc25a4
make format
amin1377 b38dbae
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 3e52cd6
[libs][arch] remove multiple definitons of e_directionality
amin1377 19452e9
[vpr][base] set type name to nullptr if type is null
amin1377 855abff
[lib][arch] fix clag warning by passing string as c_str
amin1377 ee1c9bd
[libs][arch] set fs value before calling process_tileable_device_para…
amin1377 586e56e
[libs] update submodules
amin1377 78c0583
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 326077b
[vpr][util] move find_tile_type_by_name impl under physcial_types_uti…
amin1377 4c66882
[vpr][route] move alloc_and_load_clb_to_clb_directs under clb2clb_dir…
amin1377 adec8f6
[vpr][route] fix formatting issues in tileable rr graph
amin1377 5c18569
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 abd0116
make format
amin1377 e03a84d
[vpr][tileable] move comments from cpp to .h + fix formatting
amin1377 556d499
[vpr][tileable] fix commenting style
amin1377 ec190c3
[vpr][tileable] remove const reference to ids
amin1377 78b4342
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 c6d641d
make format
amin1377 1486073
[libs][arch] move e_parallel_axis to logic_types
amin1377 0a6eb59
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 8c1729e
make format
amin1377 262ab69
[libs][rr_graph] add is_tileable to rr_graph_storage
amin1377 477103a
[route][rr_grpah] set is_tileable to true when building tileable rr g…
amin1377 5e24230
[vpr][base] add setup_vib_utils
amin1377 b6becb2
[vpr][base] create a new diretory for vib-specific grid
amin1377 1a7986a
update check_route for MUX type
amin1377 7544f77
[rr_graph] raise error if chanxy min loc is less than zero
amin1377 907565a
[libs][rr_graph] reserve capacity for node_bend_
amin1377 865b4bb
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 530f53e
Merge branch 'master' into add_tileable_rr_graph
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Original file line number | Diff line number | Diff line change |
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.. _VIB: | ||
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VIB Architecture | ||
============ | ||
The Versatile Interconnect Block (VIB) architecture adds modeling support for double-level MUX topology and bent wires. In the past, switch blocks had only one level of routing MUXes, whose inputs were driven by outputs of programmable blocks and routing tracks. Now outputs of programmable blocks can shape the first level of routing MUXes, while the inputs of second level involves the outputs of first level and other routing tracks. This can reduce the number and input sizes of routing MUXes. | ||
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Figure 1 shows the proposed VIB architecture which is tile-based. Each tile is composed of a CLB and a VIB. Each CLB can interact with the corresponding VIB which contains all the routing programmable switches in one tile. Figure 2 shows an example of the detailed interconnect architecture in VIB. The CLB input muxes and the driving muxes of wire segments can share the same fanins. A routing path of a net with two sinks is presented red in the Figure. | ||
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.. figure:: Images/VIB.png | ||
:align: center | ||
:height: 300 | ||
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Figure 1. VIB architecture. The connections between the inputs and outputs of the LB and the routing wires are all implemented within the VIB. | ||
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.. figure:: Images/double-level.png | ||
:align: center | ||
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Figure 2. Double-level MUX topology. | ||
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Figure 3 shows the modeling for bent wires. A bent L-length wire is modeled as two segments in CHANX and CHANY respectively connected by a delayless switch. The orange and red arrows represent conterclockwise and clockwise bent wires respectively. The bent wires can connect to both bent and straight wire segments. | ||
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.. figure:: Images/bent_wires.png | ||
:align: center | ||
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Figure 3. Presentation for bent wires. | ||
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FPGA Architecture File Modification (.xml) | ||
-------------------------- | ||
For the original tags available for the standard FPGA architecture file see :ref:`fpga_architecture_description`. | ||
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Modification for ``<segmentlist>`` Tag | ||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
The content within the ``<segmentlist>`` tag consists of a group of ``<segment>`` tags. | ||
The ``<segment>`` tag and its contents are described below. | ||
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.. arch:tag:: <segment axis="{x|y}" name="unique_name" length="int" type="{bidir|unidir}" res_type="{GCLK|GENERAL}" freq="float" Rmetal="float" Cmetal="float">content</segment> | ||
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:req_param content: | ||
The switch names and the depopulation pattern as described below. | ||
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.. arch:tag:: <sb type="pattern">int list</sb> | ||
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.. arch:tag:: <cb type="pattern">int list</cb> | ||
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.. arch:tag:: <mux name="string"/> | ||
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For bent wires, a new content ``<bent>`` is added in the ``<segment>`` tag. | ||
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.. arch:tag:: <cb type="pattern">bent pattern list</cb> | ||
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This tag describes the bent pattern for this particular wire segment. | ||
For example, a length 4 wire has a bent pattern of ``- - U``. | ||
A ``-`` indicates no bent at this position and a ``U`` indicates a conterclockwise bent at the position. (``D`` indicates a clockwise bent.) | ||
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.. note:: A bent wire should remain consistent in both the x and y axes. | ||
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New Added Top Level Tag ``<vib_arch>`` | ||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
The content within the ``<vib_arch>`` tag consists of a group of ``<vib>`` tags. Different ``<vib>`` tags describe the paradigms of VIB, which apply to different positions. | ||
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.. arch:tag:: <vib name="vib_name" pbtype_name="pbtype_name" vib_seg_group="int" arch_vib_switch="string">content</vib> | ||
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:req_param name: | ||
A unique alphanumeric name to identify this VIB type. | ||
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:req_param pbtype_name: | ||
The name of the block type (e.g. clb, memory) that this VIB connects to. | ||
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.. note:: A block (e.g. clb, dsp) is connected to the VIB on its top-right side, so the input and output pins of the block should be on the top or right side. | ||
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:req_param vib_seg_group: | ||
The number of the segment types in this VIB. | ||
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:req_param arch_vib_switch: | ||
Name of the mux switch type used to drive wires in the VIB by default, and a custom switch can override this switch type for specific connections if desired. | ||
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:req_param content: | ||
The segment groups and the multistage MUX topology as described below. | ||
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The ``content`` of ``<vib>`` tag consists of several ``<seg_group>`` tags and a ``<multistage_muxs>`` tag. | ||
For example: | ||
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.. code-block:: xml | ||
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<vib_arch> | ||
<vib name="vib0" pbtype_name="clb" vib_seg_group="4" arch_vib_switch="mux0"> | ||
<seg_group name="L1" track_nums="12"/> | ||
<seg_group name="L2" track_nums="20"/> | ||
<seg_group name="L4" track_nums="16"/> | ||
<seg_group name="L8" track_nums="16"/> | ||
<multistage_muxs> | ||
<first_stage switch_name="mux0"> | ||
... | ||
</first_stage> | ||
<second_stage> | ||
... | ||
</second_stage> | ||
</multistage_muxs> | ||
</vib> | ||
<vib name="vib1" pbtype_name="dsp" vib_seg_group="4" arch_vib_switch="mux0"> | ||
... | ||
</vib> | ||
</vib_arch> | ||
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.. arch:tag:: <seg_group name="seg_name" track_nums="int"/> | ||
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:req_param name: | ||
The name of the segment in this VIB described in ``<segmentlist>``. | ||
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:req_param track_nums: | ||
The track number of the segment in this VIB. | ||
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.. note:: When using unidirectional segments, the track number of the segment represents the number for one direction. For example, the ``track_nums`` is ``10``, which means total ``20`` tracks of the segment in the channel for both (INC & DEC) directions. | ||
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.. arch:tag:: <multistage_muxs>content</multistage_muxs> | ||
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:req_param content: | ||
The detailed information for first and second MUXes. | ||
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The ``content`` of ``<multistage_muxs>`` tag consists of a ``<first_stage>`` tag and a ``<secong_stage>`` tag. | ||
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.. arch:tag:: <first_stage switch_name="switch_name">content</first_stage> | ||
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:req_param switch_name: | ||
Name of the mux switch type used to drive first stage MUXes in the VIB. | ||
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:req_param content: | ||
The details of each MUX. | ||
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The ``content`` of ``<first_stage>`` tag consists of many ``<mux>`` tags. | ||
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.. arch:tag:: <mux name="mux_name">content</mux> | ||
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:req_param name: | ||
Name of the MUX. | ||
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:req_param content: | ||
A ``<from>`` tag to describe what pins and wires connect to this MUX. | ||
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For example: | ||
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.. code-block:: xml | ||
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<first_stage switch_name="mux0"> | ||
<mux name="f_mux_0"> | ||
<from>clb.O[0] clb.O[1:3] clb.O[4]</from> | ||
</mux> | ||
<mux name="f_mux_1"> | ||
<from>L1.E1 L1.S1 L2.E0</from> | ||
</mux> | ||
... | ||
</first_stage> | ||
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The ``<from>`` tag in ``<mux>`` describes nodes that connects to the MUX. ``clb.O[*]`` means output pin(s); ``L1.E1`` means the track ``1`` in the ``East`` direction of ``L1`` segment. | ||
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.. arch:tag:: <second_stage>content</second_stage> | ||
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:req_param content: | ||
The details of each MUX. | ||
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The ``content`` of ``<second_stage>`` tag consists of many ``<mux>`` tags. | ||
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.. arch:tag:: <mux name="mux_name">content</mux> | ||
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:req_param name: | ||
Name of the MUX. | ||
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:req_param content: | ||
A ``<to>`` tag to describe where this MUX connect to and a ``<from>`` tag to describe what pins and wires connect to this MUX. | ||
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For example: | ||
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.. code-block:: xml | ||
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<second_stage switch_name="mux0"> | ||
<mux name="s_mux_0"> | ||
<to>clb.I[0]</to> | ||
<from>clb.O[4] f_mux_0 f_mux_1</from> | ||
</mux> | ||
<mux name="s_mux_1"> | ||
<to>L1.E1</to> | ||
<from>L1.S2 f_mux_0 f_mux_1</from> | ||
</mux> | ||
... | ||
</second_stage> | ||
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The ``<to>`` tag describes the node this MUX connects to. ``clb.I[*]`` means input pin(s); ``L1.E1`` means the track ``1`` in the ``East`` direction of ``L1`` segment. The ``<from>`` tag in ``<mux>`` describes nodes that connects to the MUX. ``clb.O[*]`` means output pin(s); ``L1.S2`` means the track ``2`` in the ``South`` direction of ``L1`` segment. ``f_mux_0`` means the name of the specific first stage MUX. | ||
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Here is a complete example of the ``<vib>`` tag: | ||
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.. code-block:: xml | ||
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<vib name="vib_clb" pbtype_name="clb" vib_seg_group="2" arch_vib_switch="mux0"> | ||
<seg_group name="L1" track_nums="12"/> | ||
<seg_group name="L2" track_nums="20"/> | ||
<multistage_muxs> | ||
<first_stage switch_name="mux0"> | ||
<mux name="f_mux_0"> | ||
<from>clb.O[0] clb.O[1:3] clb.O[4]</from> | ||
</mux> | ||
<mux name="f_mux_1"> | ||
<from>L1.E1 L1.S1 L2.E0</from> | ||
</mux> | ||
</first_stage> | ||
<second_stage> | ||
<mux name="s_mux_0"> | ||
<to>clb.I[0]</to> | ||
<from>clb.O[4] f_mux_0 f_mux_1</from> | ||
</mux> | ||
<mux name="s_mux_1"> | ||
<to>L1.E1</to> | ||
<from>L1.S2 f_mux_0 f_mux_1</from> | ||
</mux> | ||
</second_stage> | ||
</multistage_muxs> | ||
</vib> | ||
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Its corresponding detailed architecture is shown in Figure 4. | ||
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.. figure:: Images/vib_example.png | ||
:align: center | ||
:height: 600 | ||
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Figure 4. The corresponding detaied architecture of the example. | ||
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New Added Top Level Tag ``<vib_layout>`` | ||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
Content inside this tag specifies VIB grid layout to describe different VIBs applied on different locations. | ||
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.. arch:tag:: <fixed_layout name="string">content</fixed_layout> | ||
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:req_param name: | ||
The name identifying this VIB grid layout. It should be the same as the corresponding layout name inside the ``<layout>`` tag. | ||
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:req_param content: | ||
The content should contain a set of grid location tags. For grid location tags of vib_layout see :ref:`fpga_architecture_description`; ref:`grid_expressions` | ||
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For example: | ||
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.. code-block:: xml | ||
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<vib_layout> | ||
<fixed_layout name="fixed_layout"> | ||
<perimeter type="vib_IO" priority="101"/> | ||
<fill type="vib_clb" priority="10"/> | ||
<col type="vib_memory" startx="5" starty="1" priority="100"/> | ||
... | ||
</fixed_layout> | ||
</vib_layout> | ||
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In this VIB grid layout, ``perimeter``, ``fill``, ``col`` and so on are tags in original ``<layout>`` tag to describe positions of each type of VIB block. The attribute ``type`` should correspond to the ``name`` of a ``<vib>`` tag in ``<vib_arch>``. | ||
Besides, the ``pbtype_name`` of corresponding ``<vib>`` must be the same as the physical block type at this position. | ||
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In this example, IO blocks are located on the perimeter of the layout. Memory blocks are on column 5 and CLBs are on the rest positions. The ``vib_io``, ``vib_clb`` and ``vib_memory`` are different types of vib blocks corresponding to IO, CLB and memory blocks respectively. |
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