Skip to content

Issues: verilog-to-routing/vtr-verilog-to-routing

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort

Issues list

3D SIV switch block bug
#2973 opened Apr 11, 2025 by vaughnbetz
genfasm command failing in VPR flow
#2963 opened Apr 5, 2025 by muthu-iisc
Expand y_range Search for ymax
#2959 opened Apr 1, 2025 by amin1377
Parmys Failed to load architecture file
#2927 opened Mar 11, 2025 by huma4921
Document Hermes benchmark suite
#2908 opened Feb 24, 2025 by vaughnbetz
Unable to generate odin_ii
#2879 opened Feb 3, 2025 by aryan-1307
ProTip! Add no:assignee to see everything that’s not assigned.