Add tileable RR Graph #3134

amin1377 · 2025-06-11T18:14:24Z

Merging OpenFPGA branch into master branch. PR #2135 explains features of OpenFPGA.

…le info

…rilog-to-routing into add_tileable_rr_graph

amin1377 · 2025-06-19T22:35:52Z

Hi @AlexandreSinger,

I think the PR is ready for your first round of review. I'd appreciate it if you could take a look. Thanks!

amin1377 · 2025-06-19T22:37:00Z

Hi @soheilshahrouz,

This PR is ready for your review. Since you're familiar with the RR Graph code, it would be great if you could take a look at the tileable RR Graph implementation.

…rilog-to-routing into add_tileable_rr_graph

AlexandreSinger

Hi @amin1377 thanks for bringing this in! I recognize not all of this is your code. Overall the code is well structured however it needs some code style and data structure cleanup so it can fit in better with the rest of the VTR flow.

Some. of the data structure changes can be made into issues; however, the coding style things should probably be fixed now.

doc/src/arch/reference.rst

AlexandreSinger · 2025-06-19T22:42:12Z

doc/src/arch/reference.rst

+
+.. note:: These options are required
+
+In the OpenFPGA architecture file, you may define additional attributes for each VPR's direct connection:


Are we destinguishing OpenFPGA architecture files from regular architecture files?

Based on the meeting we had before, I guess the conclusion was to not support all OpenFPGA features in the standard RR Graph generation (at least for now). As a result, I’m creating a separate section to clearly outline the additional features that are exclusively supported by the tileable RR Graph.

doc/src/arch/reference.rst

AlexandreSinger · 2025-06-19T22:46:05Z

doc/src/vpr/VIB.rst

@@ -0,0 +1,254 @@
+.. _VIB:
+
+VIB Architecture


What does VIB. I think this file also needs some context. Why is it here? Who should be using this architecture?

Good point. I moved it under the Tileable Architecture section. The vib.rst file explains what VIB is. In short, VIB combines the connection block (CB), switch block (SB), and intra-block crossbar into a single block. As a result, each tile consists of two sub-blocks: the functional block and the VIB (Versatile Interconnect Block). This design facilitates switch architecture exploration and ideally improves router flexibility.

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.h

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.cpp

amin1377 · 2025-06-23T15:06:17Z

QoR comparison:
Titan: Link
Large VTR: Link

…rilog-to-routing into add_tileable_rr_graph

… code

amin1377 · 2025-06-24T13:29:02Z

Thanks @AlexandreSinger; reviewing this amount of code is no small task, and I really appreciate your time. I've addressed your comments. Regarding your suggestions about replacing the vector of vectors with VTR data structures: while I agree with them in principle, I didn’t apply all of them since this part of the code is not performance-critical.

I think the code is now ready for the next round of reviews. I’ve also added @AmirhosseinPoolad to help with it.

soheilshahrouz

Thanks for this PR.
Since it's a large one, I’ve reviewed some files for now and will go through the rest soon.

soheilshahrouz · 2025-06-24T15:10:44Z

libs/libarchfpga/src/physical_types.h

@@ -2336,8 +2387,13 @@ struct t_arch {
    //If the layout is not specified in the command line options, this variable will be set to "auto"
    std::string device_layout;

+    std::vector<t_vib_grid_def> vib_grid_layouts;


Add a doxygen comment for this with ///

soheilshahrouz · 2025-06-24T15:14:56Z

libs/libarchfpga/src/arch_util.cpp

@@ -700,6 +700,10 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
    mem_pb_type->model_id = LogicalModelId::INVALID();

    mem_pb_type->modes[0].num_interconnect = mem_pb_type->num_ports * num_pb;
+
+    std::stringstream ss;


give a meaningful name to ss

std::string err_msg = (std::stringstream() << "Memory pb_type " << mem_pb_type->name << " has no interconnect").str(); VTR_ASSERT_MSG(mem_pb_type->modes[0].num_interconnect > 0, msg.c_str());

soheilshahrouz · 2025-06-24T15:18:17Z

libs/librrgraph/src/base/get_parallel_segs.h

@@ -13,8 +13,11 @@
 * @param segment_inf    Unified list of all segments.
 * @param seg_index_map  Map from unified to axis-specific segment indices.
 * @param parallel_axis  Axis to filter segments by.
+ * @param keep_original_index  Whether to keep the original index of the segment. Currently,
+ * it is only set to true when building the tileable rr_graph.


All @param descriptions before this are aligned. It's probably a good idea to keep them aligned

soheilshahrouz · 2025-06-24T15:19:34Z

libs/librrgraph/src/base/get_parallel_segs.cpp

@@ -2,14 +2,17 @@

 std::vector<t_segment_inf> get_parallel_segs(const std::vector<t_segment_inf>& segment_inf,
                                             t_unified_to_parallel_seg_index& seg_index_map,
-                                             enum e_parallel_axis parallel_axis) {
+                                             enum e_parallel_axis parallel_axis,
+                                             bool keep_original_index) {


Might not be a bad idea to add a comment in front of keep_original_index to mention its default value

`bool keep_original_index/=false/

soheilshahrouz · 2025-06-24T15:21:16Z

libs/librrgraph/src/base/get_parallel_segs.cpp

    std::vector<t_segment_inf> result;
    for (size_t i = 0; i < segment_inf.size(); ++i) {
        if (segment_inf[i].parallel_axis == parallel_axis || segment_inf[i].parallel_axis == BOTH_AXIS) {
            result.push_back(segment_inf[i]);
-            result[result.size() - 1].seg_index = i;
+            if (!keep_original_index) {
+                result[result.size() - 1].seg_index = i;


result.back() is more readable

soheilshahrouz · 2025-06-24T19:05:52Z

libs/librrgraph/src/base/rr_graph_storage.h

+    short node_bend_start(RRNodeId id) const {
+        return node_bend_start_[id];
+    }
+    short node_bend_end(RRNodeId id) const {


add empty line

soheilshahrouz · 2025-06-24T19:06:14Z

libs/librrgraph/src/base/rr_graph_storage.cpp

@@ -804,6 +844,9 @@ int t_rr_graph_view::node_track_num(RRNodeId id) const {
 int t_rr_graph_view::node_class_num(RRNodeId id) const {
    return get_node_class_num(node_storage_, node_ptc_, id);
 }
+int t_rr_graph_view::node_mux_num(RRNodeId id) const {


soheilshahrouz · 2025-06-24T19:06:57Z

libs/librrgraph/src/base/rr_graph_storage.cpp

+    vtr::array_view_id<RRNodeId, const t_rr_node_data> node_storage,
+    vtr::array_view_id<RRNodeId, const t_rr_node_ptc_data> node_ptc,
+    RRNodeId id) {
+    auto node_type = node_storage[id].type_;


soheilshahrouz · 2025-06-24T19:07:10Z

libs/librrgraph/src/base/rr_graph_storage.cpp

@@ -571,6 +574,11 @@ t_edge_size t_rr_graph_storage::num_non_configurable_edges(RRNodeId node, const
    return num_edges(node) - num_configurable_edges(node, rr_switches);
 }

+bool t_rr_graph_storage::edge_is_configurable(RREdgeId edge, const vtr::vector<RRSwitchId, t_rr_switch_inf>& rr_switches) const {
+  auto iswitch = edge_switch(edge);


soheilshahrouz · 2025-06-24T19:11:02Z

libs/libarchfpga/src/read_xml_arch_file.cpp

+                                        const pugiutil::loc_data& loc_data);
+
+static void process_bend(pugi::xml_node Node, std::vector<int>& list, std::vector<int>& part_len, bool& is_bend, const int len, const pugiutil::loc_data& loc_data);
+


This file is already too large
I think these functions should be moved to a new source file

amin1377 added 19 commits June 11, 2025 09:55

[vpr][rr_graph] add tileable rr graph dir

b6371d2

[vpr][rr_graph] move tileable rr graph dir uner rr_graph_generation

77781b4

[vpr][route] update rr_graph generation with tileable rr graph

cf95e2c

[vpr][util] add is_inter_cluster_node for vib arch

431923c

[vpr][route] update router lookahead with tileable rr graph

d62fb79

[vpr][blif] use regex to find param val

02a56e9

[vpr][base] update with tileable rr graph

204a794

[vpr][route] remove unused param

7edf56d

[lib][arch] add vib processing

f5e8061

[lib][arch] add vib_inf

14064c7

[libs][rr_graph] update lib rr graph with tileable

49b04b0

[libs][rr graph][io] update read/write rr graph functions with tileab…

c6df91a

…le info

[libs][rr graph][io] update rr_grpah utils with tileable info

bf19150

[lib][rr_graph] add vtr tokenizer

3970db7

[lib][util] update capnp and util with open fpga

797b488

add openfpga doc

cf2dbc8

[vpr][base] add vib grid

0e03dc7

add VIB doc

f8fae78

[vpr][route] fix alloc_and_load_rr_switch_inf definition

5462ccd

github-actions bot added VPR VPR FPGA Placement & Routing Tool libarchfpga Library for handling FPGA Architecture descriptions docs Documentation lang-cpp C/C++ code libvtrutil labels Jun 11, 2025

amin1377 added 6 commits June 11, 2025 14:15

make format

7cdf5bf

[vtr_flow][test] add openfpga arch

5ad8303

[CI] add openfpga tests

c79ab8f

fix formatting

8eccbcc

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

0cc6f10

…rilog-to-routing into add_tileable_rr_graph

[doc][arch] add tileable doc

5a492c8

amin1377 added 10 commits June 18, 2025 11:07

[doc][arch] add doc related to tileable direct interconnect

2b2fbb4

[arch] change isbend to is_bend

6e5070c

[tileable_rr_graph] fix sub_fs formatting

43ac8b4

[rr_graph] comment tileable rr_graph function under rr_graph_builder.h

5436025

[libs][rr_graph] mode bend_start/end out of t_rr_node_data

09c90f2

[base] fix function names formatting

e3df5b5

make format

e08cd8c

[libs][matrix] check for size before filling the matrix

9c87418

[libs][rr_graph] fix node_bend_start/end size

0df7730

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

837278b

…rilog-to-routing into add_tileable_rr_graph

amin1377 requested a review from AlexandreSinger June 19, 2025 22:36

amin1377 requested a review from soheilshahrouz June 19, 2025 22:37

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

7c6a979

…rilog-to-routing into add_tileable_rr_graph

AlexandreSinger requested changes Jun 20, 2025

View reviewed changes

amin1377 added 10 commits June 23, 2025 12:43

[libs][arch] fix c-style code in read_xml_arch_file

ca95008

[lib][arch] fix process_vib_block_type_locs style

bb9a338

[lib][arch] pass set funcitons params by reference

af27706

Apply code review comment

4194e81

make format

561a0d5

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

07d4bac

…rilog-to-routing into add_tileable_rr_graph

fix a typo

4e38274

[libs][arch] fix clang-17 warning

f324567

[vpr][route][tileable] replace VTR_LOG to VTR_LOG_DEBUG & fix c-style…

1f929ea

… code

[libs][vtrutil] fix string_view error

bc7ffcd

amin1377 requested a review from AmirhosseinPoolad June 24, 2025 13:29

soheilshahrouz requested changes Jun 24, 2025

View reviewed changes


		.. note:: These options are required

		In the OpenFPGA architecture file, you may define additional attributes for each VPR's direct connection:

		const pugiutil::loc_data& loc_data);

		static void process_bend(pugi::xml_node Node, std::vector<int>& list, std::vector<int>& part_len, bool& is_bend, const int len, const pugiutil::loc_data& loc_data);

Add tileable RR Graph #3134

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amin1377 commented Jun 23, 2025

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amin1377 commented Jun 11, 2025 •

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