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The code at https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/50901246919105b42a534cb58e622cada82be1bf/vpr/src/route/rr_graph2.cpp#L1225C79-L1225C90 swaps the x and y coordinates of CHANX wires when putting them in the rr_node_lookup data structure, and the find function similarly swaps them. This is baffling.
We should just put them in the lookup with their proper x,y values and the lookup function shouldn't swap them either.
It works, but the convention is bizarre, making the code less readable.
The text was updated successfully, but these errors were encountered:
soheilshahrouz
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The code at https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/50901246919105b42a534cb58e622cada82be1bf/vpr/src/route/rr_graph2.cpp#L1225C79-L1225C90 swaps the x and y coordinates of CHANX wires when putting them in the rr_node_lookup data structure, and the find function similarly swaps them. This is baffling.
Proposed Behaviour
We should just put them in the lookup with their proper x,y values and the lookup function shouldn't swap them either.
Current Behaviour
It works, but the convention is bizarre, making the code less readable.
The text was updated successfully, but these errors were encountered: