format

Author: SamuelHo10

vpr/src/draw/draw_basic.cpp

@@ -576,18 +576,16 @@ void draw_routed_net(ParentNetId net_id, ezgl::renderer* g) {
     for (auto& rt_node : route_ctx.route_trees[net_id].value().all_nodes()) {
         RRNodeId inode = rt_node.inode;
 
-        
-
-            // If a net has been highlighted, highlight all the nodes in the net the same color.
-            if (draw_if_net_highlighted(net_id)) {
-                draw_state->draw_rr_node[inode].color = draw_state->net_color[net_id];
-                draw_state->draw_rr_node[inode].node_highlighted = true;
-            } else {
-                // If not highlighted, draw the node in default color.
-                if (!draw_state->draw_rr_node[inode].node_highlighted) {
-                    draw_state->draw_rr_node[inode].color = DEFAULT_RR_NODE_COLOR;
-                }
+        // If a net has been highlighted, highlight all the nodes in the net the same color.
+        if (draw_if_net_highlighted(net_id)) {
+            draw_state->draw_rr_node[inode].color = draw_state->net_color[net_id];
+            draw_state->draw_rr_node[inode].node_highlighted = true;
+        } else {
+            // If not highlighted, draw the node in default color.
+            if (!draw_state->draw_rr_node[inode].node_highlighted) {
+                draw_state->draw_rr_node[inode].color = DEFAULT_RR_NODE_COLOR;
             }
+        }
 
         // When drawing a new branch, add the parent node to the vector to ensure that the conenction is drawn.
         if (rr_nodes_to_draw.empty() && rt_node.parent().has_value()) {

vpr/src/draw/intra_logic_block.cpp

@@ -662,14 +662,14 @@ void draw_logical_connections(ezgl::renderer* g) {
                 color = DRIVEN_BY_IT_COLOR;
             } else if (draw_state->draw_nets == DRAW_FLYLINES && draw_state->show_nets) {
                 color = ezgl::BLACK;
-                
+
                 // Turn on and off intra-cluster/inter-cluster flyline drawing based on user options
 
-                if(src_clb == sink_clb && !draw_state->draw_intra_cluster_nets) {
+                if (src_clb == sink_clb && !draw_state->draw_intra_cluster_nets) {
                     continue;
                 }
 
-                if(src_clb != sink_clb && !draw_state->draw_inter_cluster_nets) {
+                if (src_clb != sink_clb && !draw_state->draw_inter_cluster_nets) {
                     continue;
                 }
 

vpr/src/draw/intra_logic_block.h

@@ -124,7 +124,6 @@ t_selected_sub_block_info& get_selected_sub_block_info();
  */
 void draw_selected_pb_flylines(ezgl::renderer* g);
 
-
 /*
  * Draws lines from the proper logical sources, to the proper logical sinks.
  * If the draw state says to show all logical connections, it will,