Merge branch 'master' into interposer_parsing

Author: AmirhosseinPoolad

doc/src/vpr/command_line_usage.rst

@@ -840,6 +840,18 @@ If any of init_t, exit_t or alpha_t is specified, the user schedule, with a fixe
 
     **Default:** ``1.0``
 
+.. option:: --anneal_auto_init_t_estimator {cost_variance, equilibrium}
+
+   Controls which estimation method is used when selecting the starting temperature
+   for the automatic annealing schedule.
+
+   The options for estimators are:
+
+   * ``cost_variance``: Estimates the initial temperature using the variance of cost after a set of trial swaps. The initial temperature is set to a value proportional to the variance.
+   * ``equilibrium``: Estimates the initial temperature by trying to predict the equilibrium temperature for the initial placement (i.e. the temperature that would result in no change in cost).
+
+    **Default** ``cost_variance``
+
 .. option:: --init_t <float>
 
     The starting temperature of the anneal for the manual annealing schedule.

doc/src/vtr/get_vtr.rst

@@ -9,7 +9,7 @@ How to Cite
 Citations are important in academia, as they ensure contributors receive credit for their efforts.
 Therefore please use the following paper as a general citation whenever you use VTR:
 
-    M. A. Elgammal, A. Mohaghegh, S. G. Shahrouz, F. Mahmoudi, F. Koşar, K. Talaei, J. Fife, D. Khadivi, K. E. Murray, A. Boutros, K.B. Kent, J. Goeders, V. Betz "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration" ACM TRETS, 2024
+    M. A. Elgammal, A. Mohaghegh, S. G. Shahrouz, F. Mahmoudi, F. Koşar, K. Talaei, J. Fife, D. Khadivi, K. E. Murray, A. Boutros, K.B. Kent, J. Goeders, V. Betz "VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration" ACM TRETS, 2025
 
 Bibtex:
 

libs/libvqm/vqm_parser.l

@@ -40,7 +40,7 @@
 ^[ \t]*\/\/[^\n\r]*(\n|\r\n)                /* skip one-line comments */
 ^[ \t]*\(\*[^\n\r]*\*\)                     /* skip synthesis attributes and directives */
 [ \t]+                                      /* skip white spaces */
-!					    /* skip the logical operator ! applied on the input ports of the lut - this results in lut mask not being valid anoymore */
+!				    /* skip the logical operator ! applied on the input ports of the lut - this results in lut mask not being valid anoymore */
 (\n|\r\n)                                   /* skip empty lines */
 module                                      return TOKEN_MODULE;
 endmodule                                   return TOKEN_ENDMODULE;
@@ -67,6 +67,11 @@ assign                                      return TOKEN_ASSIGN;
                                                 strcpy(yylval.string, yytext+1);
                                                 return TOKEN_ESCAPEDID;
                                             }
+~\\[^ ^\t^;]+                               {
+                                                yylval.string = (char *)malloc(yyleng - 1);
+                                                strcpy(yylval.string, yytext+2);
+                                                return TOKEN_ESCAPEDID;
+                                            }
 \"[^\"]*\"                                  {
                                                 yylval.string = (char *)malloc(yyleng-1);
                                                 strncpy(yylval.string, yytext+1, yyleng-2);

utils/vqm2blif/src/base/vqm2blif_util.cpp

@@ -552,7 +552,7 @@ void generate_opname_ram (t_node* vqm_node, const LogicalModels& arch_models, st
                 reg_outputs = true;
             }
         } else {
-            VTR_ASSERT(ram_info.mode == "dual_port" || ram_info.mode == "bidir_dual_port");
+            VTR_ASSERT(ram_info.mode == "dual_port" || ram_info.mode == "bidir_dual_port" || ram_info.mode == "quad_port");
             VTR_ASSERT_MSG(ram_info.port_b_input_clock, "RAM inputs always assumed sequential");
 
             if (ram_info.mode == "dual_port" && ram_info.port_b_output_clock) {
@@ -568,6 +568,16 @@ void generate_opname_ram (t_node* vqm_node, const LogicalModels& arch_models, st
                     cout << "   port A output sequential: " << bool(ram_info.port_a_output_clock) << "\n";
                     cout << "   port B output sequential: " << bool(ram_info.port_b_output_clock) << "\n";
                 }
+            } else {
+                if (ram_info.port_a_output_clock && ram_info.port_b_output_clock) {
+                    reg_outputs = true; //Sequential output
+                } else if (!ram_info.port_a_output_clock && !ram_info.port_b_output_clock) {
+                    reg_outputs = false; //Comb output
+                } else {
+                    cout << "Unable to resolve whether quad port RAM " << vqm_node->name << " outputs are sequential or combinational:\n";
+                    cout << "   port A output sequential: " << bool(ram_info.port_a_output_clock) << "\n";
+                    cout << "   port B output sequential: " << bool(ram_info.port_b_output_clock) << "\n";
+                }
             }
         }
 
@@ -602,6 +612,8 @@ void generate_opname_ram (t_node* vqm_node, const LogicalModels& arch_models, st
         //&& (port_b_data_width == NULL) && (port_b_addr_width == NULL)) {
     if(ram_info.mode == "single_port" || ram_info.mode == "rom") {
         VTR_ASSERT(ram_info.port_b_addr_width == 0);
+        VTR_ASSERT(ram_info.port_b_addr2_width == 0);
+        VTR_ASSERT(ram_info.port_a_addr2_width == 0);
 
         //Only print the address width, the data widths are handled by the VPR memory class
         mode_hash.append(".port_a_address_width{" + std::to_string(ram_info.port_a_addr_width) + "}");
@@ -613,8 +625,9 @@ void generate_opname_ram (t_node* vqm_node, const LogicalModels& arch_models, st
         }
 
     //A dual port memory, both port A and B params have been found
-    } else {
-        VTR_ASSERT(ram_info.mode == "dual_port" || ram_info.mode == "bidir_dual_port");
+    } else if (ram_info.mode == "dual_port" || ram_info.mode == "bidir_dual_port"){
+        VTR_ASSERT(ram_info.port_b_addr2_width == 0);
+        VTR_ASSERT(ram_info.port_a_addr2_width == 0);
 
         //2) Both ports are the same size, so only append the address widths, the data widths are handled by the VPR memory class
         if (   (ram_info.port_a_data_width == ram_info.port_b_data_width)
@@ -645,6 +658,53 @@ void generate_opname_ram (t_node* vqm_node, const LogicalModels& arch_models, st
             tmp_mode_hash.append(".port_a_data_width{" + std::to_string(ram_info.port_a_data_width) + "}");
             tmp_mode_hash.append(".port_b_data_width{" + std::to_string(ram_info.port_b_data_width) + "}");
 
+            LogicalModelId arch_model_id = arch_models.get_model_by_name(tmp_mode_hash);
+            if (!arch_model_id.is_valid()) {
+                //3a) Not found, use the default name (no specific address/data widths)
+                ; // do nothing
+            } else {
+                //3b) Use the more detailed name, since it was found in the architecture
+                mode_hash = tmp_mode_hash;
+            }
+        }
+    } else {
+        VTR_ASSERT(ram_info.mode == "quad_port");
+        
+        //2) Both ports are the same size, so only append the address widths, the data widths are handled by the VPR memory class
+        if (   (ram_info.port_a_data_width == ram_info.port_b_data_width)
+            && (ram_info.port_a_addr_width == ram_info.port_b_addr_width)
+            && (ram_info.port_a_addr_width == ram_info.port_b_addr2_width)
+            && (ram_info.port_a_addr2_width == ram_info.port_b_addr2_width)) {
+
+            mode_hash.append(".port_a_address_width{" + std::to_string(ram_info.port_a_addr_width) + "}");
+            mode_hash.append(".port_a_address2_width{" + std::to_string(ram_info.port_a_addr2_width) + "}");
+            mode_hash.append(".port_b_address_width{" + std::to_string(ram_info.port_b_addr_width) + "}");
+            mode_hash.append(".port_b_address2_width{" + std::to_string(ram_info.port_b_addr2_width) + "}");
+
+            LogicalModelId arch_model_id = arch_models.get_model_by_name(mode_hash);
+            if (!arch_model_id.is_valid()) {
+                cout << "Error: could not find dual port (non-mixed_width) memory primitive '" << mode_hash << "' in architecture file";
+                exit(1);
+            }
+        //3) Mixed width dual port ram
+        } else {
+            //Make a temporary copy of the mode hash
+            string tmp_mode_hash = mode_hash;
+
+            /*
+             * Try to see if the detailed version exists in the architecture,
+             * if it does, use it.  Otherwise use the operation mode only.
+             */
+
+            tmp_mode_hash.append(".port_a_address_width{" + std::to_string(ram_info.port_a_addr_width) + "}");
+            tmp_mode_hash.append(".port_a_address2_width{" + std::to_string(ram_info.port_a_addr2_width) + "}");
+            tmp_mode_hash.append(".port_b_address_width{" + std::to_string(ram_info.port_b_addr_width) + "}");
+            tmp_mode_hash.append(".port_b_address2_width{" + std::to_string(ram_info.port_b_addr2_width) + "}");
+
+            //Each port has a different size, so print both the address and data widths. Mixed widths are not handled by the VPR memory class
+            tmp_mode_hash.append(".port_a_data_width{" + std::to_string(ram_info.port_a_data_width) + "}");
+            tmp_mode_hash.append(".port_b_data_width{" + std::to_string(ram_info.port_b_data_width) + "}");
+
             LogicalModelId arch_model_id = arch_models.get_model_by_name(tmp_mode_hash);
             if (!arch_model_id.is_valid()) {
                 //3a) Not found, use the default name (no specific address/data widths)
@@ -997,8 +1057,10 @@ RamInfo get_ram_info(const t_node* vqm_node, string device) {
     //We need to save the ram data and address widths, to identfy the RAM type (singel port, rom, simple dual port, true dual port)
     t_node_parameter* port_a_data_width = NULL;
     t_node_parameter* port_a_addr_width = NULL;
+    t_node_parameter* port_a_addr2_width = NULL;
     t_node_parameter* port_b_data_width = NULL;
     t_node_parameter* port_b_addr_width = NULL;
+    t_node_parameter* port_b_addr2_width = NULL;
 
 	for (int i = 0; i < vqm_node->number_of_params; i++){
 		//Each parameter specifies a configuration of the node in the circuit.
@@ -1020,6 +1082,11 @@ RamInfo get_ram_info(const t_node* vqm_node, string device) {
             port_a_addr_width = temp_param;
             continue;
         }
+        if (strcmp (temp_param->name, "port_a_address2_width") == 0){
+            VTR_ASSERT( temp_param->type == NODE_PARAMETER_INTEGER );
+            port_a_addr2_width = temp_param;
+            continue;
+        }
         if (strcmp (temp_param->name, "port_b_data_width") == 0){
             VTR_ASSERT( temp_param->type == NODE_PARAMETER_INTEGER );
             port_b_data_width = temp_param;
@@ -1030,6 +1097,11 @@ RamInfo get_ram_info(const t_node* vqm_node, string device) {
             port_b_addr_width = temp_param;
             continue;
         }
+        if (strcmp (temp_param->name, "port_b_address2_width") == 0){
+            VTR_ASSERT( temp_param->type == NODE_PARAMETER_INTEGER );
+            port_b_addr2_width = temp_param;
+            continue;
+        }
         if (strcmp (temp_param->name, "port_a_address_clock") == 0){ // This parameter doesn't exist for Stratix 10 - clock0 is always used for port address_a
             VTR_ASSERT( temp_param->type == NODE_PARAMETER_STRING );
             port_a_address_clock = temp_param;
@@ -1096,6 +1168,12 @@ RamInfo get_ram_info(const t_node* vqm_node, string device) {
     VTR_ASSERT(port_a_data_width);
     ram_info.port_a_data_width = port_a_data_width->value.integer_value;
 
+    if (port_a_addr2_width) {
+        ram_info.port_a_addr2_width = port_a_addr2_width->value.integer_value;
+    }
+    if (port_b_addr2_width) {
+        ram_info.port_b_addr2_width = port_b_addr2_width->value.integer_value;
+    } 
     if (port_b_addr_width) {
         ram_info.port_b_addr_width = port_b_addr_width->value.integer_value;
     }

utils/vqm2blif/src/base/vqm2blif_util.h

@@ -99,6 +99,7 @@ typedef pair <const char*, v_OptionBaseToken> tokpair;
 struct RamInfo {
     std::string mode = "";
     int port_a_addr_width = 0;
+    int port_a_addr2_width = 0;
     int port_a_data_width = 0;
     t_node_port_association* port_a_input_clock = nullptr;
     t_node_port_association* port_a_input_ena = nullptr;
@@ -108,6 +109,7 @@ struct RamInfo {
     t_node_port_association* port_a_dataout_sclr = nullptr;
 
     int port_b_addr_width = 0;
+    int port_b_addr2_width = 0;
     int port_b_data_width = 0;
     t_node_port_association* port_b_input_clock = nullptr;
     t_node_port_association* port_b_input_ena = nullptr;

vpr/src/analytical_place/full_legalizer.cpp

@@ -492,7 +492,7 @@ FlatRecon::neighbor_clustering(ClusterLegalizer& cluster_legalizer,
         if (cluster_legalizer.is_mol_clustered(molecule_id))
             continue;
 
-        // Get 8-neighbouring tile locations of the current molecule in the same layer and same type.
+        // Get 8-neighbouring tile locations of the current molecule in the same layer.
         std::vector<t_physical_tile_loc> neighbor_tile_locs;
         neighbor_tile_locs.reserve(8);
         auto [layers, width, height] = device_grid_.dim_sizes();
@@ -502,8 +502,6 @@ FlatRecon::neighbor_clustering(ClusterLegalizer& cluster_legalizer,
                 int neighbor_x = loc.x + dx, neighbor_y = loc.y + dy;
                 if (neighbor_x < 0 || neighbor_x >= (int)width || neighbor_y < 0 || neighbor_y >= (int)height)
                     continue;
-                if (device_grid_.get_physical_type(loc) != device_grid_.get_physical_type({neighbor_x, neighbor_y, loc.layer_num}))
-                    continue;
                 neighbor_tile_locs.push_back({neighbor_x, neighbor_y, loc.layer_num});
             }
         }

vpr/src/base/read_options.cpp

@@ -6,6 +6,7 @@
 #include "argparse.hpp"
 
 #include "ap_flow_enums.h"
+#include "vpr_types.h"
 #include "vtr_log.h"
 #include "vtr_path.h"
 #include "vtr_util.h"
@@ -690,6 +691,44 @@ struct ParsePlaceAgentSpace {
     }
 };
 
+struct ParsePlaceInitTEstimator {
+    ConvertedValue<e_anneal_init_t_estimator> from_str(const std::string& str) {
+        ConvertedValue<e_anneal_init_t_estimator> conv_value;
+        if (str == "cost_variance")
+            conv_value.set_value(e_anneal_init_t_estimator::COST_VARIANCE);
+        else if (str == "equilibrium")
+            conv_value.set_value(e_anneal_init_t_estimator::EQUILIBRIUM);
+        else {
+            std::stringstream msg;
+            msg << "Invalid conversion from '" << str << "' to e_anneal_init_t_estimator (expected one of: " << argparse::join(default_choices(), ", ") << ")";
+            conv_value.set_error(msg.str());
+        }
+        return conv_value;
+    }
+
+    ConvertedValue<std::string> to_str(e_anneal_init_t_estimator val) {
+        ConvertedValue<std::string> conv_value;
+        switch (val) {
+            case e_anneal_init_t_estimator::COST_VARIANCE:
+                conv_value.set_value("cost_variance");
+                break;
+            case e_anneal_init_t_estimator::EQUILIBRIUM:
+                conv_value.set_value("equilibrium");
+                break;
+            default: {
+                std::stringstream msg;
+                msg << "Unknown e_anneal_init_t_estimator type.";
+                conv_value.set_error(msg.str());
+            }
+        }
+        return conv_value;
+    }
+
+    std::vector<std::string> default_choices() {
+        return {"cost_variance", "equilibrium"};
+    }
+};
+
 struct ParseFixPins {
     ConvertedValue<e_pad_loc_type> from_str(const std::string& str) {
         ConvertedValue<e_pad_loc_type> conv_value;
@@ -2273,6 +2312,20 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
         .default_value("1.0")
         .show_in(argparse::ShowIn::HELP_ONLY);
 
+    place_grp.add_argument<e_anneal_init_t_estimator, ParsePlaceInitTEstimator>(args.place_init_t_estimator, "--anneal_auto_init_t_estimator")
+        .help(
+            "Controls which estimation method is used when selecting the starting temperature "
+            "for the automatic annealing schedule.\n"
+            "\n"
+            "The options for estimators are:\n"
+            "\tcost_variance: Estimates the initial temperature using the variance "
+            "of cost after a set of trial swaps.\n"
+            "\tequilibrium: Estimates the initial temperature by trying to "
+            "predict the equilibrium temperature for the initial placement "
+            "(i.e. the temperature that would result in no change in cost).")
+        .default_value("cost_variance")
+        .show_in(argparse::ShowIn::HELP_ONLY);
+
     place_grp.add_argument(args.PlaceInitT, "--init_t")
         .help("Initial temperature for manual annealing schedule")
         .default_value("100.0")

vpr/src/base/read_options.h

@@ -133,6 +133,7 @@ struct t_options {
     argparse::ArgValue<bool> ShowPlaceTiming;
     argparse::ArgValue<float> PlaceInnerNum;
     argparse::ArgValue<float> place_auto_init_t_scale;
+    argparse::ArgValue<e_anneal_init_t_estimator> place_init_t_estimator;
     argparse::ArgValue<float> PlaceInitT;
     argparse::ArgValue<float> PlaceExitT;
     argparse::ArgValue<float> PlaceAlphaT;

vpr/src/base/setup_vpr.cpp

@@ -729,6 +729,7 @@ static void setup_placer_opts(const t_options& Options, t_placer_opts* PlacerOpt
     PlacerOpts->placer_debug_net = Options.placer_debug_net;
 
     PlacerOpts->place_auto_init_t_scale = Options.place_auto_init_t_scale.value();
+    PlacerOpts->anneal_init_t_estimator = Options.place_init_t_estimator.value();
 }
 
 static void setup_analysis_opts(const t_options& Options, t_analysis_opts& analysis_opts) {

vpr/src/base/vpr_types.h

@@ -967,6 +967,15 @@ enum class e_place_delta_delay_algorithm {
     DIJKSTRA_EXPANSION,
 };
 
+/**
+ * @brief Enumeration of the different initial temperature estimators available
+ *        for the placer.
+ */
+enum class e_anneal_init_t_estimator {
+    COST_VARIANCE,      ///<Estimate the initial temperature using the variance in cost of a set of trial swaps.
+    EQUILIBRIUM,        ///<Estimate the initial temperature by predicting the equilibrium temperature for the initial placement.
+};
+
 enum class e_move_type;
 
 /**
@@ -1024,6 +1033,9 @@ enum class e_move_type;
  *   @param place_auto_init_t_scale
  *              When the annealer is using the automatic schedule, this option
  *              scales the initial temperature selected.
+ *   @param anneal_init_t_estimator
+ *              When the annealer is using the automatic schedule, this option
+ *              selects which estimator is used to select an initial temperature.
  */
 struct t_placer_opts {
     t_place_algorithm place_algorithm;
@@ -1097,6 +1109,8 @@ struct t_placer_opts {
     e_place_delta_delay_algorithm place_delta_delay_matrix_calculation_method;
 
     float place_auto_init_t_scale;
+
+    e_anneal_init_t_estimator anneal_init_t_estimator;
 };
 
 /******************************************************************