Merge branch 'master' into zerodiv

Author: hermanschmit

.github/scripts/run-vtr.sh

@@ -9,7 +9,8 @@ export VTR_DIR=$(pwd)
 source $SCRIPT_DIR/hostsetup.sh
 
 if ! { [ $VTR_TEST == "vtr_reg_strong" ] || [ $VTR_TEST == "odin_reg_strong" ] \
-|| [ $VTR_TEST == "odin_tech_strong" ] || [ $VTR_TEST == "vtr_reg_yosys_odin" ]; }; then
+|| [ $VTR_TEST == "odin_tech_strong" ] || [ $VTR_TEST == "vtr_reg_yosys_odin" ] \
+|| [ $VTR_TEST == "vtr_reg_yosys" ] || [ $VTR_TEST == "vtr_reg_yosys_parmys" ]; }; then
 	source $SCRIPT_DIR/vtr-full-setup.sh
 fi
 

.github/workflows/test.yml

@@ -35,7 +35,7 @@ jobs:
           - {test: "vtr_reg_strong",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3",                          extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON", extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_yosys",         cores: "16", options: "",          cmake: "-DWITH_YOSYS=ON -DYOSYS_SV_UHDM_PLUGIN=ON",     extra_pkgs: ""}
-          - {test: "vtr_reg_yosys_parmys",  cores: "16", options: "",          cmake: "-DWITH_YOSYS=ON -DYOSYS_PARMYS_PLUGIN=ON",      extra_pkgs: ""}
+          - {test: "vtr_reg_yosys_parmys",  cores: "16", options: "",          cmake: "-DWITH_YOSYS=ON -DYOSYS_PARMYS_PLUGIN=ON -DYOSYS_SV_UHDM_PLUGIN=ON",      extra_pkgs: ""}
           - {test: "vtr_reg_yosys_odin",    cores: "16", options: "",          cmake: "-DODIN_USE_YOSYS=ON -DYOSYS_SV_UHDM_PLUGIN=ON", extra_pkgs: ""}
           - {test: "odin_tech_strong",      cores: "16", options: "",          cmake: "-DODIN_USE_YOSYS=ON",                           extra_pkgs: ""}
           - {test: "odin_reg_strong",       cores: "16", options: "",          cmake: "",                                              extra_pkgs: ""}

ODIN_II/CMakeLists.txt

@@ -154,7 +154,10 @@ add_library(libodin_ii STATIC
 
 # link libyosys to the Odin-II library
 if(${ODIN_USE_YOSYS})
-    target_link_libraries(libodin_ii libyosys)
+    add_dependencies(libodin_ii libyosys)
+    target_link_directories(libodin_ii PUBLIC ${VTR_SOURCE_DIR}/build/libs/EXTERNAL/libyosys)
+    target_include_directories(libodin_ii PUBLIC ${VTR_SOURCE_DIR}/Yosys/share/yosys/include)
+    target_link_libraries(libodin_ii yosys)
 endif()
 
 target_include_directories(libodin_ii PUBLIC ${LIB_INCLUDE_DIRS})
@@ -224,3 +227,4 @@ if(VTR_ENABLE_STRICT_COMPILE)
 endif()
 
 install(TARGETS odin_II libodin_ii DESTINATION bin)
+install(FILES ${LIB_HEADERS_H} ${LIB_HEADERS_HPP} DESTINATION include/libodin_ii)

ODIN_II/SRC/BLIF.cpp

@@ -1,5 +1,5 @@
-/**
- * Copyright (c) 2021 Seyed Alireza Damghani ([email protected])
+/*
+ * Copyright 2023 CAS—Atlantic (University of New Brunswick, CASA)
  * 
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -21,8 +21,6 @@
  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
- *
- * @file the definition of the BLIF class constructor, destructor
  */
 
 #include "BLIF.hpp"

ODIN_II/SRC/BLIFElaborate.cpp

@@ -1,5 +1,5 @@
-/**
- * Copyright (c) 2021 Seyed Alireza Damghani ([email protected])
+/*
+ * Copyright 2023 CAS—Atlantic (University of New Brunswick, CASA)
  * 
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -21,14 +21,6 @@
  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
- *
- * @file a netlist traversal phase newly added to Odin-II techmap.
- * Basically, this file includes the resolve_XXX_node routines to
- * make high-level netlist nodes compatible with Odin-II partial 
- * mapper. However, the instantiation process of operations that 
- * aren't supported by Odin-II synthesis flow is also implemented
- * in this phase. 
- * E.g. Division (constant, variable), Exponentiation (variable) 
  */
 
 #include <string.h>

ODIN_II/SRC/BLIFReader.cpp

@@ -1,5 +1,6 @@
-/**
- *
+/*
+ * Copyright 2023 CAS—Atlantic (University of New Brunswick, CASA)
+ * 
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
  * files (the "Software"), to deal in the Software without
@@ -20,14 +21,6 @@
  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
- *
- * @file: includes the definition of BLIF Reader class to read a given
- * BLIF file. The Odin-II BLIF Reader can also read large files since 
- * it read each file with a BLIF_READ_BUFFER chunk or line by line.
- * Odin-II BLIF Reader caches the read models while traversing the
- * BLIF file to avoid searching the BLIF file looking for the model 
- * definition. Moreover, function getbline provides developers with 
- * the ability to read a BLIF file line by line or using a chunk.
  */
 
 #include <stdlib.h>

ODIN_II/SRC/BLIFWriter.cpp

@@ -1,4 +1,6 @@
-/**
+/*
+ * Copyright 2023 CAS—Atlantic (University of New Brunswick, CASA)
+ * 
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
  * files (the "Software"), to deal in the Software without
@@ -19,12 +21,6 @@
  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
- *
- * @file: definition of BLIF Writer routine to generate a BLIF output 
- * file. Unlike other tools that print each BLIF record in a single 
- * line, Odin-II BLIF Writer prints BLIF records in a specified size. 
- * That means it makes the BLIF file more readable by splitting the 
- * line by the specified threshold. 
  */
 
 #include <stdlib.h>

ODIN_II/SRC/BitwiseOps.cpp

@@ -1,5 +1,5 @@
-/**
- * Copyright (c) 2022 Seyed Alireza Damghani ([email protected])
+/*
+ * Copyright 2023 CAS—Atlantic (University of New Brunswick, CASA)
  * 
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -21,9 +21,6 @@
  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
- *
- * @file: This file provides utilities to modify the bitwise nodes 
- * to make them compatible with the Odin-II partial mapper.
  */
 
 #include <cmath> // log2

ODIN_II/SRC/BlockMemories.cpp

@@ -1,5 +1,5 @@
-/**
- * Copyright (c) 2021 Seyed Alireza Damghani ([email protected])
+/*
+ * Copyright 2023 CAS—Atlantic (University of New Brunswick, CASA)
  * 
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -21,17 +21,6 @@
  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
- *
- * @file: This file includes the definitions of the routines to map 
- * block memories to VTR compatible memory types, i.e., Single Port RAM 
- * and Dual Port RAM. The definition of block memory and read-only memory
- * is provided in techlib directory in the Odin-II root directory. 
- * Basically, a memory block with both read and write accesses that has a
- * separate port for each operation is called BRAM. While following the 
- * same definition, a read-only memory block is referred to as a BRAM that
- * has only read access (even multiple accesses). This function also 
- * includes ymem block support which somehow represents the Yosys internal
- * memory cell.
  */
 
 #include <string.h>
@@ -68,6 +57,7 @@ static void create_r2w_dual_port_ram(block_memory_t* bram, netlist_t* netlist);
 static void create_2rw_dual_port_ram(block_memory_t* bram, netlist_t* netlist);
 static void create_2r2w_dual_port_ram(block_memory_t* bram, netlist_t* netlist);
 static void create_nrmw_dual_port_ram(block_memory_t* bram, netlist_t* netlist);
+static void create_2rw_multiplexed_dual_port_ram(block_memory_t* bram, netlist_t* netlist);
 
 static nnode_t* ymem_to_rom(nnode_t* node, uintptr_t traverse_mark_number);
 static nnode_t* ymem2_to_rom(nnode_t* node, uintptr_t traverse_mark_number);
@@ -850,11 +840,6 @@ static void create_2rw_dual_port_ram(block_memory_t* bram, netlist_t* netlist) {
         add_pin_to_signal_list(rd_data2, bram->read_data->pins[i + offset]);
     }
 
-    /* delete rd pins since we use corresponding wr_en and zero*/
-    for (i = 0; i < bram->read_en->count; ++i) {
-        delete_npin(bram->read_en->pins[i]);
-    }
-
     /**
      * [NOTE]:
      * Odin-II handle memory block with more than two distint
@@ -874,11 +859,16 @@ static void create_2rw_dual_port_ram(block_memory_t* bram, netlist_t* netlist) {
             free_signal_list(rd_data2);
 
             /* all ports have different address */
-            create_nrmw_dual_port_ram(bram, netlist);
+            create_2rw_multiplexed_dual_port_ram(bram, netlist);
             return;
         }
     }
 
+    /* delete rd pins since we use corresponding wr_en and zero*/
+    for (i = 0; i < bram->read_en->count; ++i) {
+        delete_npin(bram->read_en->pins[i]);
+    }
+
     /* map matched read data to the out1 */
     signals->out1 = (first_match) ? rd_data1 : rd_data2;
 
@@ -979,11 +969,6 @@ static void create_2r2w_dual_port_ram(block_memory_t* bram, netlist_t* netlist)
         add_pin_to_signal_list(rd_data2, bram->read_data->pins[i + offset]);
     }
 
-    /* delete rd pins since we use corresponding wr_en and zero*/
-    for (i = 0; i < bram->read_en->count; ++i) {
-        delete_npin(bram->read_en->pins[i]);
-    }
-
     /**
      * [NOTE]:
      * Odin-II handle memory block with more than two distint
@@ -1012,6 +997,11 @@ static void create_2r2w_dual_port_ram(block_memory_t* bram, netlist_t* netlist)
         return;
     }
 
+    /* delete rd pins since we use corresponding wr_en and zero*/
+    for (i = 0; i < bram->read_en->count; ++i) {
+        delete_npin(bram->read_en->pins[i]);
+    }
+
     /* create a list of dpram ram signals */
     dp_ram_signals* signals = (dp_ram_signals*)vtr::malloc(sizeof(dp_ram_signals));
 
@@ -1163,6 +1153,88 @@ static void create_nrmw_dual_port_ram(block_memory_t* bram, netlist_t* netlist)
     free_dp_ram_signals(signals);
 }
 
+/**
+ * (function: create_2rw_multiplexed_dual_port_ram)
+ * 
+ * @brief read ports are multiplexed using read enable.
+ * multiple write ports are multiplexed using write enable.
+ * Then, the BRAM will be mapped to a DPRAM
+ * 
+ * @param bram pointing to a bram node node
+ * @param netlist pointer to the current netlist file
+ */
+static void create_2rw_multiplexed_dual_port_ram(block_memory_t* bram, netlist_t* netlist) {
+    int i;
+    nnode_t* old_node = bram->node;
+    int data_width = bram->node->attributes->DBITS;
+    int addr_width = bram->node->attributes->ABITS;
+    int num_rd_ports = old_node->attributes->RD_PORTS;
+    int num_wr_ports = old_node->attributes->WR_PORTS;
+
+    /* should have been resovled before this function */
+    oassert(num_rd_ports == 2);
+    oassert(num_wr_ports == 1);
+
+    /* dual port ram signals */
+    dp_ram_signals* signals = (dp_ram_signals*)vtr::calloc(1, sizeof(dp_ram_signals));
+    signal_list_t* selectors = NULL;
+
+    /* INPUTS */
+    selectors = copy_input_signals(bram->read_en);
+    /* adding the read addr input port as address1 */
+    signals->addr1 = split_cascade_port(bram->read_addr,
+                                        selectors,
+                                        addr_width,
+                                        old_node,
+                                        netlist);
+    free_signal_list(selectors);
+
+    signals->addr2 = init_signal_list();
+    for (i = 0; i < bram->write_addr->count; ++i) {
+        add_pin_to_signal_list(signals->addr2, bram->write_addr->pins[i]);
+    }
+
+    /* handling clock signals */
+    signals->clk = bram->clk->pins[0];
+
+    /* we pad the first data port using pad pins */
+    signals->data1 = init_signal_list();
+    for (i = 0; i < data_width; ++i) {
+        add_pin_to_signal_list(signals->data1, get_pad_pin(netlist));
+    }
+
+    signals->data2 = init_signal_list();
+    for (i = 0; i < data_width; ++i) {
+        add_pin_to_signal_list(signals->data2, bram->write_data->pins[i]);
+    }
+
+    /* first port does not have data, so the enable is GND */
+    signals->we1 = get_zero_pin(netlist);
+
+    signals->we2 = bram->write_en->pins[0];
+
+    /* OUTPUT */
+    /* leaving out1 of dpram null, so it will create a new pins */
+    signals->out1 = NULL;
+    signals->out2 = NULL;
+
+    /* create a DPRAM node */
+    nnode_t* dpram = create_dual_port_ram(signals, old_node);
+
+    signal_list_t* dpram_outputs = init_signal_list();
+    for (i = 0; i < data_width; ++i) {
+        add_pin_to_signal_list(dpram_outputs, dpram->output_pins[i]);
+    }
+
+    /* decode the spram outputs to the n bram output ports */
+    decode_out_port(dpram_outputs, bram->read_data, bram->read_en, old_node, netlist);
+
+    // CLEAN UP
+    cleanup_block_memory_old_node(old_node);
+    free_signal_list(dpram_outputs);
+    free_dp_ram_signals(signals);
+}
+
 /**
  * (function: map_rom_to_mem_hardblocks)
  * 
@@ -2234,4 +2306,4 @@ static void free_block_memory(block_memory_t* to_free) {
     vtr::free(to_free->memory_id);
 
     vtr::free(to_free);
-}
+}

ODIN_II/SRC/CaseEqual.cpp

@@ -1,5 +1,5 @@
-/**
- * Copyright (c) 2021 Seyed Alireza Damghani ([email protected])
+/*
+ * Copyright 2023 CAS—Atlantic (University of New Brunswick, CASA)
  * 
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -21,10 +21,6 @@
  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
- *
- * @file: this file includes the circuitry implementation of case_equal 
- * and case_not_equal high-level netlist nodes. The implementations 
- * are XNOR, AND and invertor gates based. 
  */
 
 #include "CaseEqual.hpp"