riffpga -- write FPGA bitstreams through a USB drive, get USB serial and dynamic clocking in a platform independent way
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Updated
Feb 8, 2025 - C
riffpga -- write FPGA bitstreams through a USB drive, get USB serial and dynamic clocking in a platform independent way
Simple Ping Pong game on Xilinx Spartan 3E
A pipelined Symmetric FIR (Finite Impulse Response) filter implementation in Verilog HDL.
Undergraduate level RISC-V microcontroller
Verilog code to implement 8 bit full adder and demonstration of the result on FPGA board.
Verilog Code to Implementation on FPGA of 8 Bit Signed Multiplier
T20 Cricket Game using Verilog coding. Includes a constraint file for implementing on Nexys A7 FPGA board.
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