Issue#1503: Added new rules for structure and alignment of multiline signal initialisations

docs/configuring_array_multiline_structure_rules.rst

@@ -566,5 +566,6 @@ Rules Enforcing Array Multiline Structure Rules
 * `concurrent_012 <concurrent_rules.html#concurrent-012>`_
 * `constant_016 <constant_rules.html#constant-016>`_
 * `sequential_009 <sequential_rules.html#sequential-009>`_
+* `signal_403 <signal_rules.html#signal-403>`_
 * `variable_403 <variable_rules.html#variable-403>`_
 * `variable_assignment_008 <variable_assignment_rules.html#variable-assignment-008>`_

docs/configuring_keyword_alignment_rules.rst

@@ -989,6 +989,7 @@ Rules Enforcing Keyword Alignment
 * `protected_type_body_401 <protected_type_body_rules.html#protected-type-body-401>`_
 * `protected_type_body_402 <protected_type_body_rules.html#protected-type-body-402>`_
 * `sequential_400 <sequential_rules.html#sequential-400>`_
+* `signal_401 <signal_rules.html#signal-401>`_
 * `subprogram_body_400 <subprogram_body_rules.html#subprogram-body-400>`_
 * `subprogram_body_401 <subprogram_body_rules.html#subprogram-body-401>`_
 * `type_400 <type_rules.html#type-400>`_

docs/configuring_multiline_indent_rules.rst

@@ -127,6 +127,7 @@ Rules Enforcing Multiline Indent Rules
 * `sequential_004 <sequential_rules.html#sequential-004>`_
 * `sequential_402 <sequential_rules.html#sequential-402>`_
 * `signal_400 <signal_rules.html#signal-400>`_
+* `signal_402 <signal_rules.html#signal-402>`_
 * `variable_400 <signal_rules.html#variable-400>`_
 * `variable_402 <variable_rules.html#variable-402>`_
 * `variable_assignment_004 <variable_assignment_rules.html#variable-assignment-004>`_

docs/rule_groups/alignment_rule_group.rst

@@ -75,6 +75,8 @@ Rules Enforcing Alignment Rule Group
 * `sequential_402 <../sequential_rules.html#sequential-402>`_
 * `signal_012 <../signal_rules.html#signal-012>`_
 * `signal_400 <../signal_rules.html#signal-400>`_
+* `signal_401 <../signal_rules.html#signal-401>`_
+* `signal_402 <../signal_rules.html#signal-402>`_
 * `subprogram_body_400 <../subprogram_body_rules.html#subprogram-body-400>`_
 * `subprogram_body_401 <../subprogram_body_rules.html#subprogram-body-401>`_
 * `type_400 <../type_rules.html#type-400>`_

docs/rule_groups/structure_rule_group.rst

@@ -173,6 +173,8 @@ Rules Enforcing Structure Rule Group
 * `signal_007 <../signal_rules.html#signal-007>`_
 * `signal_015 <../signal_rules.html#signal-015>`_
 * `signal_017 <../signal_rules.html#signal-017>`_
+* `signal_018 <../signal_rules.html#signal-018>`_
+* `signal_403 <../signal_rules.html#signal-403>`_
 * `source_file_001 <../source_file_rules.html#source-file-001>`_
 * `subprogram_instantiation_001 <../subprogram_instantiation_rules.html#subprogram-instantiation-001>`_
 * `subprogram_instantiation_002 <../subprogram_instantiation_rules.html#subprogram-instantiation-002>`_

docs/signal_rules.rst

@@ -334,6 +334,31 @@ This rule checks the structure of signal constraints.
        element2(3 downto 0)
      );
 
+signal_018
+##########
+
+|phase_1| |error| |structure|
+
+This rule checks the **:=** is on the same line as the **signal** keyword.
+
+**Violation**
+
+.. code-block:: vhdl
+
+   signal size : integer
+      := 1;
+   signal width : integer
+      := 32;
+
+**Fix**
+
+.. code-block:: vhdl
+
+   signal size    : integer :=
+     1;
+   signal width   : integer :=
+     32;
+
 signal_100
 ##########
 
@@ -456,6 +481,96 @@ This rule checks alignment of multiline constraints in signal declarations.
        element2(3 downto 0)
      );
 
+signal_401
+##########
+
+|phase_5| |error| |alignment|
+
+This rule checks the alignment of assignment keywords in signal declarations.
+
+|configuring_keyword_alignment_rules_link|
+
+**Violation**
+
+.. code-block:: vhdl
+
+   signal c_default_values : t_address_en := (
+     c_address_control => false,
+     c_address_data => true,
+     others => false
+   );
+
+**Fix**
+
+.. code-block:: vhdl
+
+   signal c_default_values : t_address_en := (
+     c_address_control => false,
+     c_address_data    => true,
+     others            => false
+   );
+
+signal_402
+##########
+
+|phase_5| |error| |alignment|
+
+This rule checks the alignment of multiline signal initializations that contain arrays.
+
+|configuring_multiline_indent_rules_link|
+
+.. NOTE:: The structure of multiline array signal initializations is handled by the rule `signal_403 <signal_rules.html#signal-403>`_.
+
+**Violation**
+
+.. code-block:: vhdl
+
+   signal rom : romq_type :=
+   (
+            0,
+        65535,
+        32768
+     );
+
+**Fix**
+
+.. code-block:: vhdl
+
+   signal rom : romq_type :=
+   (
+     0,
+     65535,
+     32768
+   );
+
+signal_403
+##########
+
+|phase_5| |error| |structure|
+
+This rule checks the structure of multiline signal initializations that contain arrays.
+
+|configuring_array_multiline_structure_rules_link|
+
+.. NOTE:: The indenting of multiline array signal initializations is handled by the rule `signal_402 <signal_rules.html#signal-402>`_.
+
+**Violation**
+
+.. code-block:: vhdl
+
+   signal rom : romq_type := (0, 65535, 32768);
+
+**Fix**
+
+.. code-block:: vhdl
+
+   signal rom : romq_type :=
+   (
+     0,
+     65535,
+     32768
+   );
+
 signal_600
 ##########
 

tests/signal/rule_018_test_input.fixed.vhd

@@ -0,0 +1,41 @@
+
+architecture RTL of FIFO is
+
+  signal width : integer;
+
+  signal width : integer := 16;
+
+  signal depth : integer :=
+   512;
+
+  signal AVMM_MASTER_NULL  : avmm_master_t := (
+    (others => '0'),
+    (others => '0'),
+    '0',
+    '0'
+  );
+
+  --! Test stimulus
+    SIGNAL stimulus : t_stimulus_array :=
+
+    (
+        (
+            name      => "Hold in reset       ",
+            clk_in    => "0101010101010101",
+            rst_in    => "1111111111111111",
+            cnt_en_in => "0000000000000000",
+            cnt_out   => "0000000000000000"
+        ),
+        (
+            name      => "Not enabled         ",
+            clk_in    => "0101010101010101",
+            rst_in    => "0000000000000000",
+            cnt_en_in => "0000000000000000",
+            cnt_out   => "0000000000000000"
+        )
+   );
+
+
+begin
+
+end architecture RTL;

tests/signal/rule_018_test_input.vhd

@@ -0,0 +1,41 @@
+
+architecture RTL of FIFO is
+
+  signal width : integer;
+
+  signal width : integer := 16;
+
+  signal depth : integer
+  := 512;
+
+  signal AVMM_MASTER_NULL  : avmm_master_t := (
+    (others => '0'),
+    (others => '0'),
+    '0',
+    '0'
+  );
+
+  --! Test stimulus
+    SIGNAL stimulus : t_stimulus_array
+:=
+    (
+        (
+            name      => "Hold in reset       ",
+            clk_in    => "0101010101010101",
+            rst_in    => "1111111111111111",
+            cnt_en_in => "0000000000000000",
+            cnt_out   => "0000000000000000"
+        ),
+        (
+            name      => "Not enabled         ",
+            clk_in    => "0101010101010101",
+            rst_in    => "0000000000000000",
+            cnt_en_in => "0000000000000000",
+            cnt_out   => "0000000000000000"
+        )
+   );
+
+
+begin
+
+end architecture RTL;

tests/signal/rule_400_test_input.fixed__align_left_no__align_paren_no.vhd

@@ -19,10 +19,10 @@ architecture rtl of fifo is
                              );
 
   signal s : MY_TYPE := (
-                         a => '0',
-                         ddddd => (others => '0'),
-                         ffff => (others => '0')
-                        );
+                    a => '0',
+                                ddddd => (others => '0'),
+                            ffff => (others => '0')
+                );
 
   signal AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
                            ar_addr(AddrRange_c), aw_addr(AddrRange_c),

tests/signal/rule_400_test_input.fixed__align_left_no__align_paren_yes.vhd

@@ -19,10 +19,10 @@ architecture rtl of fifo is
                              );
 
   signal s : MY_TYPE := (
-                         a => '0',
-                         ddddd => (others => '0'),
-                         ffff => (others => '0')
-                        );
+                    a => '0',
+                                ddddd => (others => '0'),
+                            ffff => (others => '0')
+                );
 
   signal AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
                            ar_addr(AddrRange_c), aw_addr(AddrRange_c),

tests/signal/rule_400_test_input.fixed__align_left_yes__align_paren_no.vhd

@@ -19,10 +19,10 @@ architecture rtl of fifo is
   );
 
   signal s : MY_TYPE := (
-    a => '0',
-    ddddd => (others => '0'),
-    ffff => (others => '0')
-  );
+                    a => '0',
+                                ddddd => (others => '0'),
+                            ffff => (others => '0')
+                );
 
   signal AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
     ar_addr(AddrRange_c), aw_addr(AddrRange_c),

tests/signal/rule_400_test_input.fixed__align_left_yes__align_paren_yes.vhd

@@ -19,10 +19,10 @@ architecture rtl of fifo is
   );
 
   signal s : MY_TYPE := (
-    a => '0',
-    ddddd => (others => '0'),
-    ffff => (others => '0')
-  );
+                    a => '0',
+                                ddddd => (others => '0'),
+                            ffff => (others => '0')
+                );
 
   signal AxiMs : axi_ms_t (ar_id(IdRange_c), aw_id(IdRange_c),
     ar_addr(AddrRange_c), aw_addr(AddrRange_c),