Version 5.2.0

HISTORY.md

@@ -104,3 +104,5 @@
   - Added `PAD_*` constants for combined button and Control Pad masks
   - Added `B_COLOR_*` red/green/blue bit numbers
   - Corrected comments on `B_BG_PRIO` and `B_OAM_PRIO`
+- **Rev 6.0.0** - 2025-06-30 *(Rangi42)*
+  - Changed `_AUD3WAVERAM` to `AUD3WAVERAM`

hardware.inc

@@ -22,7 +22,7 @@ endc
 ; Define the include guard and the current hardware.inc version
 ; (do this after the RGBDS version check since the `def` syntax depends on it)
 def HARDWARE_INC equ 1
-def HARDWARE_INC_VERSION equs "5.1.0"
+def HARDWARE_INC_VERSION equs "6.0.0"
 
 ; Usage: rev_Check_hardware_inc <min_ver>
 ; Examples:
@@ -66,7 +66,7 @@ def B_JOYP_DOWN   equ 3 ; 0 = Down is pressed   (if reading Control Pad) [ro]
 def B_JOYP_UP     equ 2 ; 0 = Up is pressed     (if reading Control Pad) [ro]
 def B_JOYP_LEFT   equ 1 ; 0 = Left is pressed   (if reading Control Pad) [ro]
 def B_JOYP_RIGHT  equ 0 ; 0 = Right is pressed  (if reading Control Pad) [ro]
-    def JOYP_INPUTS equ %0000_1111
+    def JOYP_INPUTS equ %0000_1111 ; 0 bits are pressed (if reading inputs)
     def JOYP_START  equ 1 << B_JOYP_START
     def JOYP_SELECT equ 1 << B_JOYP_SELECT
     def JOYP_B      equ 1 << B_JOYP_B
@@ -422,7 +422,7 @@ def B_AUDENA_ENABLE_CH1 equ 0 ; 1 = channel 1 is running [ro]
 
 ; -- AUD3WAVE ($FF30-$FF3F) ---------------------------------------------------
 ; Audio channel 3 wave pattern RAM [r/w]
-def _AUD3WAVERAM equ $FF30 ; $FF30-$FF3F
+def AUD3WAVERAM equ $FF30 ; $FF30-$FF3F
 
 def rAUD3WAVE_0 equ $FF30
 def rAUD3WAVE_1 equ $FF31
@@ -441,7 +441,7 @@ def rAUD3WAVE_D equ $FF3D
 def rAUD3WAVE_E equ $FF3E
 def rAUD3WAVE_F equ $FF3F
 
-def AUD3WAVE_SIZE equ 16
+def AUD3WAVE_SIZE equ 16 ; size of wave pattern RAM in bytes
 
 ; -- LCDC ($FF40) -------------------------------------------------------------
 ; PPU graphics control
@@ -606,7 +606,7 @@ def rVDMA_SRC_LOW equ $FF52
 ; (CGB only) VRAM DMA destination address (high 8 bits) [wo]
 def rVDMA_DEST_HIGH equ $FF53
 
-; -- VDMA_DEST_LOW / HDMA3 ($FF54) --------------------------------------------
+; -- VDMA_DEST_LOW / HDMA4 ($FF54) --------------------------------------------
 ; (CGB only) VRAM DMA destination address (low 8 bits) [wo]
 def rVDMA_DEST_LOW equ $FF54
 
@@ -868,12 +868,14 @@ def RAMREG_ENABLE equ $40
 ; Latch accelerometer start [wo]
 def rACCLATCH0 equ $A000
 
+; Write $55 to ACCLATCH0 to erase the latched data
 def ACCLATCH0_START equ $55
 
 ; -- ACCLATCH1 ($Ax1x) --------------------------------------------------------
 ; Latch accelerometer finish [wo]
 def rACCLATCH1 equ $A010
 
+; Write $AA to ACCLATCH1 to latch the accelerometer and update ACCEL*
 def ACCLATCH1_FINISH equ $AA
 
 ; -- ACCELX0 ($Ax2x) ----------------------------------------------------------
@@ -903,6 +905,7 @@ def rEEPROM equ $A080
 ; IR register [r/w]
 def rIRREG equ $A000
 
+; whether the IR transmitter sees light
 def IR_LED_OFF equ $C0
 def IR_LED_ON  equ $C1
 

hardware_compat.inc

@@ -139,6 +139,8 @@ def AUD2HIGHF_PERIOD_HIGH equ AUD2HIGH_PERIOD_HIGH
 
 def AUD3ENAB_ENABLE equ B_AUD3ENA_ENABLE
 
+def _AUD3WAVERAM equ AUD3WAVERAM
+
 def AUD3LEVELF_VOLUME equ AUD3LEVEL_VOLUME
 
 def AUD3HIGHB_RESTART     equ B_AUD3HIGH_RESTART