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Verilog: KNOWNBUG test for assert ... else #1308

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Merged
merged 1 commit into from
Oct 10, 2025
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Verilog: KNOWNBUG test for assert ... else #1308

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9 changes: 9 additions & 0 deletions regression/verilog/SVA/assert_else1.desc
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Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
KNOWNBUG
assert_else1.sv
--module main
^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
This doesn't parse.
9 changes: 9 additions & 0 deletions regression/verilog/SVA/assert_else1.sv
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Original file line number Diff line number Diff line change
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module main(input clk);

task some_task;
$fatal("property failed");
endtask;

assert property (0) else some_task();

endmodule
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