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Pull requests: diffblue/hw-cbmc

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Pull requests list

extract SVA_to_LTL(exprt) into a separate file cleanup
#1098 opened May 3, 2025 by kroening Loading…
SMV netlists: use TRUE/FALSE instead of 1/0
#1097 opened May 2, 2025 by kroening Loading…
BDD engine: transform SVA to LTL, then LTL to CTL engines Verilog
#1096 opened May 2, 2025 by kroening Loading…
implement NNF for SVA s_always engines Verilog
#1095 opened May 2, 2025 by kroening Loading…
SMV: convert typecasts to SMV SMV
#1094 opened May 1, 2025 by kroening • Draft
SMV: introduce classes for extend, resize, signed, unsigned SMV
#1093 opened May 1, 2025 by kroening Loading…
SVA [*...] for sequence operands Verilog
#1092 opened Apr 30, 2025 by kroening Loading…
introduce sva_boolean_exprt Verilog
#1083 opened Apr 23, 2025 by kroening • Draft
introduce verilog_sva_property_typet Verilog
#1081 opened Apr 23, 2025 by kroening • Draft
SMV: expression typechecker now post-traversal SMV
#1040 opened Mar 28, 2025 by kroening Loading…
2
SVA monitor engines Verilog
#1011 opened Feb 25, 2025 by kroening • Draft
SystemVerilog: --initial-zero Verilog
#1001 opened Feb 20, 2025 by kroening Loading…
6
SystemVerilog: interface instantiation Verilog
#972 opened Feb 6, 2025 by kroening • Draft
SystemVerilog: declarations in named blocks in tasks/functions Verilog
#970 opened Feb 6, 2025 by kroening • Draft
1
SystemVerilog: preserve scopes between compilation units Verilog
#963 opened Feb 4, 2025 by kroening • Draft
SystemVerilog: create identifier expressions in scanner Verilog
#953 opened Jan 29, 2025 by kroening • Draft
Add chipsalliance/sv-tests to CI
#939 opened Jan 17, 2025 by kroening • Draft
aval/bval lowering for reduction operators Verilog
#930 opened Jan 16, 2025 by kroening • Draft
vlindex: fix parsing for constraint_block
#924 opened Jan 6, 2025 by kroening • Draft
SystemVerilog: fix identifier on enum type Verilog
#919 opened Jan 2, 2025 by kroening • Draft
liveness engine engines
#915 opened Dec 29, 2024 by kroening • Draft
SMV: clean up parse tree SMV
#909 opened Dec 27, 2024 by kroening • Draft
SMV: typechecking for ?: SMV
#906 opened Dec 26, 2024 by kroening • Draft
SMV: typechecking for unary minus SMV
#893 opened Dec 20, 2024 by kroening • Draft
SystemVerilog: type parameter ports Verilog
#842 opened Nov 21, 2024 by kroening • Draft
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