Skip to content

NeurIPS 2025 SystemVerilog benchmarks #1147

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: main
Choose a base branch
from
Open

NeurIPS 2025 SystemVerilog benchmarks #1147

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
The table of contents is too big for display.
Diff view
Diff view
  •  
  •  
  •  
35 changes: 35 additions & 0 deletions examples/NeurIPS2025/Liveness/PWM_1-l1.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);

localparam CBITS = 10; // Change pulse_wideR accordingly

wire [CBITS-1:0] pulse_wideR;
assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 5'd0}; // (CBTIS-5)
assign lbR = {1'b0, 4'b0000, 1'b1, 5'd0};
assign ubR = {1'b0, 4'b1111, 1'b1, 5'd0};

reg [CBITS-1:0] cnt_R;

always @(posedge clk) begin
cnt_R <= cnt_R + 1;

if (cnt_R < pulse_wideR)
pulse_red = 1;
else
pulse_red = 0;

if (cnt_R < lbR)
lb_pulse = 1;
else
lb_pulse = 0;

if (cnt_R < ubR)
ub_pulse = 1;
else
ub_pulse = 0;
end


// LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
assert property (@(posedge clk) always s_eventually pulse_red == 0);

endmodule
35 changes: 35 additions & 0 deletions examples/NeurIPS2025/Liveness/PWM_10-l1.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);

localparam CBITS = 19; // Change pulse_wideR accordingly

wire [CBITS-1:0] pulse_wideR;
assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 14'd0}; // (CBTIS-5)
assign lbR = {1'b0, 4'b0000, 1'b1, 14'd0};
assign ubR = {1'b0, 4'b1111, 1'b1, 14'd0};

reg [CBITS-1:0] cnt_R;

always @(posedge clk) begin
cnt_R <= cnt_R + 1;

if (cnt_R < pulse_wideR)
pulse_red = 1;
else
pulse_red = 0;

if (cnt_R < lbR)
lb_pulse = 1;
else
lb_pulse = 0;

if (cnt_R < ubR)
ub_pulse = 1;
else
ub_pulse = 0;
end


// LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
assert property (@(posedge clk) always s_eventually pulse_red == 0);

endmodule
35 changes: 35 additions & 0 deletions examples/NeurIPS2025/Liveness/PWM_11-l1.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);

localparam CBITS = 20; // Change pulse_wideR accordingly

wire [CBITS-1:0] pulse_wideR;
assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 15'd0}; // (CBTIS-5)
assign lbR = {1'b0, 4'b0000, 1'b1, 15'd0};
assign ubR = {1'b0, 4'b1111, 1'b1, 15'd0};

reg [CBITS-1:0] cnt_R;

always @(posedge clk) begin
cnt_R <= cnt_R + 1;

if (cnt_R < pulse_wideR)
pulse_red = 1;
else
pulse_red = 0;

if (cnt_R < lbR)
lb_pulse = 1;
else
lb_pulse = 0;

if (cnt_R < ubR)
ub_pulse = 1;
else
ub_pulse = 0;
end


// LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
assert property (@(posedge clk) always s_eventually pulse_red == 0);

endmodule
35 changes: 35 additions & 0 deletions examples/NeurIPS2025/Liveness/PWM_12-l1.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);

localparam CBITS = 21; // Change pulse_wideR accordingly

wire [CBITS-1:0] pulse_wideR;
assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 16'd0}; // (CBTIS-5)
assign lbR = {1'b0, 4'b0000, 1'b1, 16'd0};
assign ubR = {1'b0, 4'b1111, 1'b1, 16'd0};

reg [CBITS-1:0] cnt_R;

always @(posedge clk) begin
cnt_R <= cnt_R + 1;

if (cnt_R < pulse_wideR)
pulse_red = 1;
else
pulse_red = 0;

if (cnt_R < lbR)
lb_pulse = 1;
else
lb_pulse = 0;

if (cnt_R < ubR)
ub_pulse = 1;
else
ub_pulse = 0;
end


// LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
assert property (@(posedge clk) always s_eventually pulse_red == 0);

endmodule
35 changes: 35 additions & 0 deletions examples/NeurIPS2025/Liveness/PWM_2-l1.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);

localparam CBITS = 11; // Change pulse_wideR accordingly

wire [CBITS-1:0] pulse_wideR;
assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 6'd0}; // (CBTIS-5)
assign lbR = {1'b0, 4'b0000, 1'b1, 6'd0};
assign ubR = {1'b0, 4'b1111, 1'b1, 6'd0};

reg [CBITS-1:0] cnt_R;

always @(posedge clk) begin
cnt_R <= cnt_R + 1;

if (cnt_R < pulse_wideR)
pulse_red = 1;
else
pulse_red = 0;

if (cnt_R < lbR)
lb_pulse = 1;
else
lb_pulse = 0;

if (cnt_R < ubR)
ub_pulse = 1;
else
ub_pulse = 0;
end


// LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
assert property (@(posedge clk) always s_eventually pulse_red == 0);

endmodule
35 changes: 35 additions & 0 deletions examples/NeurIPS2025/Liveness/PWM_3-l1.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);

localparam CBITS = 12; // Change pulse_wideR accordingly

wire [CBITS-1:0] pulse_wideR;
assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 7'd0}; // (CBTIS-5)
assign lbR = {1'b0, 4'b0000, 1'b1, 7'd0};
assign ubR = {1'b0, 4'b1111, 1'b1, 7'd0};

reg [CBITS-1:0] cnt_R;

always @(posedge clk) begin
cnt_R <= cnt_R + 1;

if (cnt_R < pulse_wideR)
pulse_red = 1;
else
pulse_red = 0;

if (cnt_R < lbR)
lb_pulse = 1;
else
lb_pulse = 0;

if (cnt_R < ubR)
ub_pulse = 1;
else
ub_pulse = 0;
end


// LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
assert property (@(posedge clk) always s_eventually pulse_red == 0);

endmodule
35 changes: 35 additions & 0 deletions examples/NeurIPS2025/Liveness/PWM_4-l1.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);

localparam CBITS = 13; // Change pulse_wideR accordingly

wire [CBITS-1:0] pulse_wideR;
assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 8'd0}; // (CBTIS-5)
assign lbR = {1'b0, 4'b0000, 1'b1, 8'd0};
assign ubR = {1'b0, 4'b1111, 1'b1, 8'd0};

reg [CBITS-1:0] cnt_R;

always @(posedge clk) begin
cnt_R <= cnt_R + 1;

if (cnt_R < pulse_wideR)
pulse_red = 1;
else
pulse_red = 0;

if (cnt_R < lbR)
lb_pulse = 1;
else
lb_pulse = 0;

if (cnt_R < ubR)
ub_pulse = 1;
else
ub_pulse = 0;
end


// LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
assert property (@(posedge clk) always s_eventually pulse_red == 0);

endmodule
35 changes: 35 additions & 0 deletions examples/NeurIPS2025/Liveness/PWM_5-l1.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);

localparam CBITS = 14; // Change pulse_wideR accordingly

wire [CBITS-1:0] pulse_wideR;
assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 9'd0}; // (CBTIS-5)
assign lbR = {1'b0, 4'b0000, 1'b1, 9'd0};
assign ubR = {1'b0, 4'b1111, 1'b1, 9'd0};

reg [CBITS-1:0] cnt_R;

always @(posedge clk) begin
cnt_R <= cnt_R + 1;

if (cnt_R < pulse_wideR)
pulse_red = 1;
else
pulse_red = 0;

if (cnt_R < lbR)
lb_pulse = 1;
else
lb_pulse = 0;

if (cnt_R < ubR)
ub_pulse = 1;
else
ub_pulse = 0;
end


// LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
assert property (@(posedge clk) always s_eventually pulse_red == 0);

endmodule
35 changes: 35 additions & 0 deletions examples/NeurIPS2025/Liveness/PWM_6-l1.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);

localparam CBITS = 15; // Change pulse_wideR accordingly

wire [CBITS-1:0] pulse_wideR;
assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 10'd0}; // (CBTIS-5)
assign lbR = {1'b0, 4'b0000, 1'b1, 10'd0};
assign ubR = {1'b0, 4'b1111, 1'b1, 10'd0};

reg [CBITS-1:0] cnt_R;

always @(posedge clk) begin
cnt_R <= cnt_R + 1;

if (cnt_R < pulse_wideR)
pulse_red = 1;
else
pulse_red = 0;

if (cnt_R < lbR)
lb_pulse = 1;
else
lb_pulse = 0;

if (cnt_R < ubR)
ub_pulse = 1;
else
ub_pulse = 0;
end


// LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
assert property (@(posedge clk) always s_eventually pulse_red == 0);

endmodule
35 changes: 35 additions & 0 deletions examples/NeurIPS2025/Liveness/PWM_7-l1.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);

localparam CBITS = 16; // Change pulse_wideR accordingly

wire [CBITS-1:0] pulse_wideR;
assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 11'd0}; // (CBTIS-5)
assign lbR = {1'b0, 4'b0000, 1'b1, 11'd0};
assign ubR = {1'b0, 4'b1111, 1'b1, 11'd0};

reg [CBITS-1:0] cnt_R;

always @(posedge clk) begin
cnt_R <= cnt_R + 1;

if (cnt_R < pulse_wideR)
pulse_red = 1;
else
pulse_red = 0;

if (cnt_R < lbR)
lb_pulse = 1;
else
lb_pulse = 0;

if (cnt_R < ubR)
ub_pulse = 1;
else
ub_pulse = 0;
end


// LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
assert property (@(posedge clk) always s_eventually pulse_red == 0);

endmodule
Loading
Loading