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SystemVerilog: const #1063

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Merged
merged 1 commit into from
Apr 15, 2025
Merged

SystemVerilog: const #1063

merged 1 commit into from
Apr 15, 2025

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kroening
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@kroening kroening commented Apr 12, 2025

This adds a check that the LHS of assignments is not const.

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tiennou Etienne Samson
This adds a check that the LHS of assignments is not const.
@kroening kroening changed the title SystemVerilog: const SystemVerilog: const Apr 13, 2025
@kroening kroening marked this pull request as ready for review April 14, 2025 00:13
@@ -94,6 +94,7 @@ IREP_ID_ONE(sva_implies)
IREP_ID_ONE(sva_not)
IREP_ID_ONE(sva_or)
IREP_ID_ONE(module_instance)
IREP_ID_TWO(C_const, #const)
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Shouldn't we just use C_constant from CBMC? Over there, it's used for exactly the same purpose.

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Yes, but it's mis-named. There is nothing constant about const variables.

Ideally, I'd like to rename #constant into #c_const.

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I agree with the mis-naming. I obviously don't intend to block this PR, but I'd prefer to see a medium-term cleanup of this across the two code bases.

@kroening kroening merged commit aac75f1 into main Apr 15, 2025
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@kroening kroening deleted the verilog-const branch April 15, 2025 16:38
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2 participants