Update TB for BNW s2 bug + remove recv_aborted_by_reset protocol

tests/fpga-debugging/axi-stream-s2/expects/s2_buggy.bi.expect

@@ -14,12 +14,5 @@ error: [recv@411?] executing step 1 of the transaction: 1 != 0
 50 │       assert_eq(DUT.M_AXIS_TLAST, is_last);
    │       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [recv@411?] executing step 1 of the transaction: 1 != 0
 
-
-error: [recv_aborted_by_reset@411?] executing step 1 of the transaction: 1 != 0
-   ┌─ tests/fpga-debugging/axi-stream-s2/s2.prot:83:7
-   │
-83 │       assert_eq(DUT.M_AXIS_TLAST, is_last);
-   │       ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [recv_aborted_by_reset@411?] executing step 1 of the transaction: 1 != 0
-
 ---CODE---
 1

tests/fpga-debugging/axi-stream-s2/expects/s2_fixed.bi.expect

@@ -7,6 +7,4 @@ trace {
     recv(4, 15, 0, 0);  // [time: 937.5ns -> 962.5ns]
     recv(5, 15, 0, 0);  // [time: 962.5ns -> 987.5ns]
     recv(6, 15, 0, 0);  // [time: 987.5ns -> 1012.5ns]
-    recv_aborted_by_reset(7, 15, 0, 2);  // [time: 1012.5ns -> 1087.5ns]
-    reset();  // [time: 1087.5ns -> 1087.5ns]
 }

tests/fpga-debugging/axi-stream-s2/s2.prot

@@ -55,38 +55,3 @@ prot recv<DUT: AXISManager>(data: u32, strb: u4, is_last: u1, backpressure: uint
     step();
 }
 
-// Models a receive that never makes it to the end.
-// This is a special version of the normal receive in order to represent what it happening
-// at the end of the "fixed" trace. It is unclear what the AXIS spec has to say on this, but it seems
-// a bit like an unintentional behavior on the test bench's side.
-prot recv_aborted_by_reset<DUT: AXISManager>(data: u32, strb: u4, is_last: u1, backpressure: uint) {
-    // no reset during transaction
-    DUT.M_AXIS_ARESETN := 1'b1;
-
-    // wait until sender sets data to valid, before that applying backpressure is OK but meaningless
-    while (!(DUT.M_AXIS_TVALID == 1'b1)) {
-        step();
-    }
-
-    // now check data that is being sent
-    assert_eq(DUT.M_AXIS_TDATA, data);
-    assert_eq(DUT.M_AXIS_TSTRB, strb);
-    assert_eq(DUT.M_AXIS_TLAST, is_last);
-
-    // we apply n cycles of backpressure, during these, the valid signal and the data may not change
-    DUT.M_AXIS_TREADY := 1'b0;
-    repeat backpressure iterations {
-      step();
-      assert_eq(DUT.M_AXIS_TVALID, 1'b1);
-      assert_eq(DUT.M_AXIS_TDATA, data);
-      assert_eq(DUT.M_AXIS_TSTRB, strb);
-      assert_eq(DUT.M_AXIS_TLAST, is_last);
-    }
-
-    // instead of being accepted, the transaction is canceled by reset
-    DUT.M_AXIS_ARESETN := 1'b0;
-    step();
-}
-
-
-