docs: ad4170_asdz: Fixed documentation #1715
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ladace
requested review from
IuliaCMoldovan,
gastmaier,
StancaPop and
LBFFilho
as code owners
StancaPop
requested changes
May 9, 2025
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v1:
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StancaPop
requested changes
May 12, 2025
docs/projects/ad4170_asdz/index.rst
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| The HDL reference design for the :adi:`AD4170-4` and :adi:`AD4170-8` provides a | ||
| high resolution, 24-Bit, DC to 50 kHz Input Bandwidth, Multichannel, Low Noise | ||
| Precision Sigma-Delta ADC with PGA. | ||
| The HDL reference design for the :adi:`AD4170-4` provides a high resolution, |
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| The HDL reference design for the :adi:`AD4170-4` provides a high resolution, | |
| The HDL reference design for the :adi:`AD4170-4` provides a high resolution, |
docs/projects/ad4170_asdz/index.rst
Outdated
| high resolution, 24-Bit, DC to 50 kHz Input Bandwidth, Multichannel, Low Noise | ||
| Precision Sigma-Delta ADC with PGA. | ||
| The HDL reference design for the :adi:`AD4170-4` provides a high resolution, | ||
| 24-Bit, DC to 50 kHz Input Bandwidth, Multichannel, Low Noise Precision |
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| 24-Bit, DC to 50 kHz Input Bandwidth, Multichannel, Low Noise Precision | |
| 24-Bit, DC to 50 kHz Input Bandwidth, Multichannel, Low Noise Precision |
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StancaPop
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docs/projects/ad4170_asdz/index.rst
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| :adi:`AD4190-4` provides a high resolution, 24-Bit, Multichannel, Low Noise, | ||
| Precision Sigma-Delta ADC with PGA. | ||
| The HDL reference design for the :adi:`AD4170-4` :adi:`AD4190-4`provides | ||
| a high resolution, 24-Bit, DC to 50 kHz Input Bandwidth, Multichannel, |
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| a high resolution, 24-Bit, DC to 50 kHz Input Bandwidth, Multichannel, | |
| a high resolution, 24-Bit, DC to 50 kHz Input Bandwidth, Multichannel, |
docs/projects/ad4170_asdz/index.rst
Outdated
| @@ -66,7 +63,7 @@ The addresses are dependent on the architecture of the FPGA, having an offset | |||
| added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). | |||
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| ======================== ================= | |||
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| ======================== ================= | |
| ======================== =============== |
docs/projects/ad4170_asdz/index.rst
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| @@ -66,7 +63,7 @@ The addresses are dependent on the architecture of the FPGA, having an offset | |||
| added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). | |||
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| ======================== ================= | |||
| Instance Zynq*/DE10-Nano** | |||
| Instance Zynq/DE10-Nano | |||
| ======================== ================= | |||
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| ======================== ================= | |
| ======================== =============== |
Fixed documentation and removed not yet released ADC parts. Signed-off-by: Liviu 'Ceshu' Adace <[email protected]>
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V2:
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StancaPop
approved these changes
May 21, 2025
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PR Description
Fixed documentation and removed not yet released parts
PR Type
PR Checklist