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Remove REG_WIDTH from AxiTop
fletchgenFletchgen related issueFletchgen related issueStatus: Open.#266 In abs-tudelft/fletcher;Mismatch between bus address width and addresses passed through vhdmmio
bugSomething isn't workingSomething isn't workingfletchgenFletchgen related issueFletchgen related issueStatus: Open.#243 In abs-tudelft/fletcher;Use an existing standard for start/stop/reset MMIO control registers
enhancementNew feature or requestNew feature or requestStatus: Open.#193 In abs-tudelft/fletcher;AXI read/write converter broken when slices depth > 0
bugSomething isn't workingSomething isn't workinglang:vhdlVHDL related issueVHDL related issueStatus: Open.#164 In abs-tudelft/fletcher;Wrap AxiTop into an AxiTopSim for simulation
enhancementNew feature or requestNew feature or requestfletchgenFletchgen related issueFletchgen related issueStatus: Open.#135 In abs-tudelft/fletcher;Prevent ambiguity among Arrow data stream signals
hardwareHardware related issueHardware related issueStatus: Open.#123 In abs-tudelft/fletcher;Multi-clock domain support incomplete
enhancementNew feature or requestNew feature or requesthardwareHardware related issueHardware related issueStatus: Open.#93 In abs-tudelft/fletcher;Arrow implicit null bitmap is not propagated during run time
enhancementNew feature or requestNew feature or requesthardwareHardware related issueHardware related issueruntimeRuntime related issueRuntime related issueStatus: Open.#66 In abs-tudelft/fletcher;