Writers currently do not properly support separate clock domains for the bus and accellerator, despite availability of separate clock/reset ports. The read side should support it, though enabling the CDC logic is inconveniently done for each reader separately through the CFG string. Multi-clock-domain test code should also be created or improved.
Writers currently do not properly support separate clock domains for the bus and accellerator, despite availability of separate clock/reset ports. The read side should support it, though enabling the CDC logic is inconveniently done for each reader separately through the CFG string. Multi-clock-domain test code should also be created or improved.