[WS1][CUDA][Qwen3-Next] C6: GDN decode-step goldens and recurrent/conv state contract (RFC #428 stack 4/4)

[fusheng-ji]

Repository refactor update

Merged RL-Align/RL-Kernel:test-qwennext at a5a92ecf6cbf29fdcfc862846e53db5fa244c35e as requested in RFC #428. This PR still targets test-qwennext.

Implementation changes now live in the canonical rl_engine/backends, rl_engine/reference, rl_engine/runtime, and rl_engine/validation directories. Where present, model assembly and vLLM training bridges use rl_engine/models/qwen3_next and rl_engine/integrations/engines/train/vllm, respectively. Tests use tests/models/qwen3_next; evidence and validation commands use tools/validation/models and tools/validation/operators. Existing upstream compatibility entry points and pinned operator identifiers are preserved. CI commands and path filters follow the new layout, including the test-qwennext target.

Validation after migration: 298 passed, 73 skipped in the relevant regression suites. CUDA tests used extensions built from the matching migrated native sources on B200. Syntax, undefined-name/duplicate-import checks, formatting, and git diff --check passed.

Status [2026-10-08]

• Since tip 0b41350 named in the Latest Status below, the branch merged test-qwennext (c883134) and, on 2026-10-08, the aligned [WS1][CUDA][Qwen3-Next] Gated RMSNorm CUDA kernel for the GDN block (RFC #428 stack 3/4) #468 (490499c, c214004), which brings [WS1][CUDA][Qwen3-Next] C1: zero-centred RMSNorm references and CUDA kernel (RFC #428 stack 2/4) #467's latest fixes and the norm evidence. At 490499c with two B200s: 283 passed (72 skipped, all Ascend) across the GDN state contract and norm suites, tests/check_gdn_recurrent_golden.py plus tests/check_qwen3_next_norm_providers.py 40 passed, and the four Qwen3-Next C3/C4 gates pass. The older results under Test results predate these merges.
• Added: L1 for the conv golden (db420ab, test_conv_golden_is_batch_invariant). The recurrent L1 test covers four rows of one batch of 64 at one seed; the new conv test runs every sequence of a batch of 257 alone, plus sub-batches of 2, 7 and 64 at other offsets and a shuffled batch order, with contiguous and shuffled cache blocks, fp32 and bf16 caches, with and without bias and SiLU, over three seeds. Output rows and rolled state blocks are bitwise unchanged in all 8 configurations, and a deliberately batch-dependent golden fails it. tests/check_gdn_recurrent_golden.py: 39 passed.

Latest Status [2026-10-04]

2026-10-04, later: re-stacked onto #468 (cf68fd9, on #467 d03c852 and #466 6a4f078, which adds the
device guard a maintainer asked for in the CUDA RMSNorm launchers). This PR's 20 commits replay unchanged
(same git patch-id relative to #468); the tree differs from the previous tip only by #466's change.
Commit ids below are the replayed ones.

Ready for review. Top of a four-PR stack for #428, on top of
feat/cuda-qwen3-next-gated-rmsnorm (#468, tip cf68fd9), which is itself on
feat/cuda-qwen3-next-c1-norm (#467) and fix/registry-cuda-rmsnorm-dispatch (#466). All three
must merge first. Tip 0b41350.

2026-10-04: the maintainers retargeted the stack to test-qwennext and asked for conflicts to be
resolved; re-stacked onto #468 (cf68fd9, on test-qwennext 11cac8c) with every commit signed off
(DCO). The branch used to take the gated branch in through three merges; it is now linear: the
18 commits of this PR replayed in order, plus one commit, 395fef8, that carries the
ci/run_ws1_gtest.sh reconciliation those merges had produced. The patch relative to #468 is
identical to the one measured below (git patch-id), and the final tree is byte-identical to the
pre-rebase tip. f8d9399 adds two runner sections (conv_silu, conv_noact_bf16) that locate the
fp32-cache conv mismatches, and 610f1b7 rewrites design note §4 to state the two mechanisms they
measured. The test results below were measured before the re-stack; 32b765e..11cac8c on the base is
formatting, lint/docs/CI configuration and the logp indexed-write fix, none of which changes the
arithmetic measured here. The diff shown by GitHub includes the three lower PRs' commits until they merge.

2026-10-04, later: CodeRabbit (requested review) found that _chunked_sum fell back to a plain
.sum for a last dimension that is not a multiple of 32, which is not fixed-order. 0b41350 pads
to the next 32 boundary instead, so every width reduces in the same chunk order, and adds a CPU
test for an odd width (test_gdn_state_contract.py:112-124). Qwen3-Next has K=V=128, so none of
the numbers below change; the line references to gated_delta_rule.py below _chunked_sum moved
by four lines and were refreshed.

Repository file:line refer to this branch (0b41350; 395fef8 touches only
ci/run_ws1_gtest.sh, 0b41350 only _chunked_sum and the CPU test). vLLM paths are relative to the installed vllm 0.30.0 package root. Two
files are named causal_conv1d.py: the golden is
rl_engine/kernels/ops/pytorch/linear_attn/causal_conv1d.py, the provider is vLLM's
model_executor/layers/mamba/ops/causal_conv1d.py; each citation says which.

Merge request: please squash-merge this PR's own commits (the 20 listed below).

Summary

Bitwise status: advances C6 of #428 (GDN recurrent response replay) with two
PyTorch goldens for the Qwen3-Next decode step and a GDN cache-state contract. There is no
CUDA kernel in this PR. Claim level L0 + L1 for the PyTorch goldens; L2 is not
claimed.

• L1 is the golden against itself: in one batch of 64 (seed 3, all rows active), rows
  0, 1, 31 and 63 produce bitwise the same output and state block when run alone, for fp32
  and bf16 state. No L1 claim is made for the provider.
• Asserted bitwise against vLLM: the conv update's rolled state (torch.equal,
  B ∈ {1, 4, 17, 64} × fp32/bf16 cache) and one hand-built, bias-free cancellation input.
• Not bitwise against vLLM: the recurrent golden is close to
  fused_recurrent_gated_delta_rule_packed_decode but not equal to it (fp32 state, measured:
  max|d out| up to 6.10e-5, max|d state| up to 2.98e-7; one seed per batch, random inputs, no
  real weights; asserted ≤ 1e-3 / ≤ 1e-5). With an fp32 conv cache, a few conv output
  elements differ (measured: at most 5 of 524,288; asserted ≤ 32 elements). The cause is
  Triton's SiLU (ex2.approx, div.full.f32) against PyTorch's exp and IEEE division, not
  the convolution; measured by the runner's conv_silu section (Notes).
• The packed kernel is the provider only in decode-only steps. A reported observation
  with no runner in this PR (standalone layer, synthetic parameters) found that, in vLLM 0.30.0's default configuration, whether a
  prefill shares the step changes a decode row's state, and at TP4 per-rank head counts its
  output too (Notes).
• L2: the real-checkpoint startup attempt (vLLM 0.30.0, 2026-09-30) failed before
  inference with VLLM batch_invariant mode is not supported for GDN_ATTN
  (docs/design/rfc428-c6-gdn-recurrent-replay.md:299-303, labelled there as a reported
  observation). Op-level agreement says nothing about 48 composed layers.

• Target provider. A decode-only, non-speculative step returns early into
  _forward_core_decode_non_spec (model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py:1295-1307)
  because VLLM_ENABLE_FLA_PACKED_RECURRENT_DECODE defaults to on (envs.py:1199-1200), so
  the recurrent golden targets fused_recurrent_gated_delta_rule_packed_decode, not
  fused_sigmoid_gating_delta_rule_update. VLLM_GDN_DECODE_KERNEL="cuda" is not what
  Qwen3-Next runs: gqa_interleaved_layout=True (model_executor/models/qwen3_next.py:495)
  makes the layer fall back to "triton" (qwen_gdn_linear_attn.py:520-523). Steps shared
  with a prefill go through causal_conv1d_fn and fused_sigmoid_gating_delta_rule_update
  instead; this golden does not target those (Notes).
• The golden follows the kernel's arithmetic, not modeling_qwen3_next.py's, checked
  line by line against third_party/flash_linear_attention/ops/fused_recurrent.py:288-335:
  fused fp32 gating with the softplus threshold at 20, no repeat_interleave
  (i_h = i_hv // (HV // H)), and the QK norm x / sqrt(sum(x*x) + 1e-6) with scale on
  q after the norm. Softplus and the reduction order are not transcriptions (Notes).
• State ABI. Recurrent state [num_blocks, HV, V, K] addressed by ssm_state_indices
  with an fp32 accumulator; the store rounds to the state dtype (fp32 or bf16,
  FUSED_GDN_STATE_DTYPES, qwen_gdn_linear_attn.py:91). Conv state [num_blocks, dim, W-1]
  or the transposed "SD" layout (dim_first). The goldens raise on an active index that is
  out of range or repeated (gated_delta_rule.py:61-73); the providers check neither.
  NULL_BLOCK_ID is not one contract across the two providers (Notes).
• The conv half of the decode step. RFC §9.1 files causal-convolution exactness under
  C4; the decode-step conv update is here because RFC §7.2's row reads "Trainer calls the
  rollout update at the same boundary", and in rollout conv update and recurrent step make one
  decode step. It can be split out to C4 if maintainers prefer. CausalConv1dUpdateOp starts
  the fp32 accumulator from bias and rounds each tap product to the operand dtype first
  (golden causal_conv1d.py:167-177), as the provider does (vLLM causal_conv1d.py:960-967,
  1000).
• bf16 recurrent state is a differential experiment; the strict profile uses fp32 (design
  note :262-263). Not in this PR: speculative decode / MTP, backward (RFC [RFC][Qwen3-Next-80B-A3B-Instruct][CUDA/ROCm] VIME/vLLM operator-level train-rollout consistency roadmap, ablation matrix, and integration plan #428 C7;
  supports_backward=false), a registry entry, the paged allocator, TP sharding, ROCm/Ascend,
  and the prefill side (Notes).
• Changes to existing code: .github/workflows/ci.yml's unit-tests list gains
  tests/test_gdn_state_contract.py (ci.yml:70); a new self-hosted workflow runs the two
  check_ files. ws1-gtest-gpu.yml and ci/run_ws1_gtest.sh are as on the gated branch.

Prior art & reuse decision

N/A: this PR adds PyTorch goldens and a cache-state contract, not an operator implementation, so the reuse rule does not apply. The goldens are compared against vLLM's own GDN paths in the Summary above.

Files

file	commit	status
rl_engine/kernels/ops/pytorch/linear_attn/gated_delta_rule.py	ef4c88d, dbb8d00, dcb9263, 1d69312	GatedDeltaRuleRecurrentStepOp; index validation (:61-73); _softplus NaN-gradient fix (dcb9263); NULL_BLOCK_ID comment and two duplicate index checks dropped (1d69312)
rl_engine/kernels/ops/pytorch/linear_attn/causal_conv1d.py	ef4c88d, dbb8d00, 1d69312	CausalConv1dUpdateOp; bias-first, product-rounded accumulation (:167-177)
rl_engine/kernels/ops/pytorch/linear_attn/__init__.py	ef4c88d, dbb8d00	exports (new)
tests/check_gdn_recurrent_golden.py	ef4c88d, dbb8d00, 697bea8, 2d895d0, 1d69312	31 cases against vLLM (new; not collected by default); _RECURRENT_BOUNDS (:60-65), dims from FINGERPRINT (:42-48)
tests/test_gdn_state_contract.py	dbb8d00, dcb9263, 1d69312	19 CPU cases (new); SPDX header (1d69312)
scripts/ws1_gdn_provider_agreement.py	b54ac72, 9da9c36, 10e5230, 1d69312, f8d9399	runner behind the measured numbers (new)
docs/design/rfc428-c6-gdn-recurrent-replay.md	ef4c88d, dbb8d00, 7b30633, 5216a6c, 2d895d0, 52f7f61, 7862a12, 1d69312, c0ab21c, 610f1b7	design note "RFC #428 C6" (new; renamed in 1d69312)
.github/workflows/qwen3-next-provider-gpu.yml	16204ab, 12a2225, 1d69312	self-hosted provider workflow (new)
.github/workflows/ci.yml	1d69312	test_gdn_state_contract.py added to the unit-tests list

commit	what
ef4c88d	the two goldens, their tests, the design note
dbb8d00	cache-index validation and tests/test_gdn_state_contract.py; conv products rounded to the operand dtype before fp32 accumulation; withdraws the earlier 1024-step and prefill tables (no checked-in runner)
dcb9263	_softplus: the untaken branch's gradient was NaN once exp(x) exceeds the fp32 range (x ≳ 88.7), and that NaN leaked through torch.where. Fixed
16204ab	CI: the self-hosted workflow qwen3-next-provider-gpu.yml, which runs the two check_ files
697bea8	test: the packed-decode provider leaves the null block untouched
12a2225	CI: drops stale and forward-referencing workflow paths; ws1-gtest-gpu.yml is back to the gated branch's version
b54ac72	scripts/ws1_gdn_provider_agreement.py
7b30633	design note corrected against the vLLM 0.30.0 source
9da9c36, 10e5230	runner fixes: unknown git state recorded as null; a real fusion-off arm and SASS FFMA counts
5216a6c, 2d895d0, 52f7f61, 7862a12	design note and test docstring: backward deferral, measured agreement, the FP-contraction result, the mixed-step caveat's scope
1d69312	review fixes: runner usage writes to $TMPDIR (F1); unreproduced §5/§7 numbers labelled (F2); every bound labelled a regression bound, with the contract's reduction row for scale (F3); ci.yml list (F4); note renamed and retitled "RFC #428 C6", backward written "RFC #428 C7" (F6); one _RECURRENT_BOUNDS constant read by the test and the runner (F10); dims from FINGERPRINT (F11); provenance records rl_engine.__file__, FLA_USE_FAST_OPS, TRITON_DEFAULT_FP_FUSION (F12); workflow header, concurrency, fork notice, _C location check (F13); NULL_BLOCK_ID comment (F14); two duplicate index checks dropped, so a 2-D index now raises the validator's message (F17); SPDX header (F20)
c0ab21c	design note: four in-repo line references refreshed after the gated-branch merge and 1d69312 moved their targets; no line count change
f8d9399	runner: conv_silu and conv_noact_bf16 sections, which locate the fp32-cache conv mismatches; the PTX counts gain the packed f32x2 forms, ex2.approx and div.full.f32; fusion_check covers every variant an arm compiles
395fef8	ci/run_ws1_gtest.sh as the former merges of the gated branch had reconciled it; the re-stack replays dbb8d00's version of that file first and this commit restores the merged result (final tree unchanged)
610f1b7	design note §4: the two conv mismatch mechanisms, measured by the runner at f8d9399; the recurrent provider's Triton exp/sigmoid noted as open
0b41350	_chunked_sum pads a last dimension that is not a multiple of 32 to the next chunk boundary instead of falling back to an unordered .sum (CodeRabbit finding on #469); CPU test for an odd width

Test

MAX_JOBS=32 TORCH_CUDA_ARCH_LIST=10.0 RL_KERNEL_REQUIRE_EXT=1 \
    pip install --no-build-isolation --no-deps -e .
python -m pytest tests/check_gdn_recurrent_golden.py -q -p no:randomly   # needs CUDA + vLLM 0.30.0
python -m pytest tests/test_gdn_state_contract.py -q -p no:randomly
# regression on the PRs below
python -m pytest tests/test_qwen3_next_norm.py -q -p no:randomly
python -m pytest tests/check_qwen3_next_norm_providers.py -q -p no:randomly   # needs vLLM 0.30.0
python -m pytest tests/test_qwen3_next_workload.py -q -p no:randomly
python -m pytest rl_engine/tests/test_dispatch.py -q -p no:randomly
python -m pytest tests/test_rms_norm.py tests/test_ws1_gtest_gpu.py tests/test_vjp_fp32.py -q -p no:randomly
python -m pytest tests/ rl_engine/tests/ -q -p no:randomly -rfE \
    --ignore=tests/test_rocm_aiter_api_contract.py
python scripts/check_operator.py --op rms_norm --candidate cuda --device cuda --dtype bf16 \
    --batch 2 --seq 16 --normalized-dim 4096 --seed 123 --check-grad
python scripts/check_operator.py --op rms_norm_gated --candidate cuda --device cuda --dtype bf16 \
    --batch 2 --seq 16 --head-dim 128 --seed 123 --check-grad
python scripts/check_operator.py --op qwen3_next_rms_norm --candidate cuda --device cuda --dtype bf16 \
    --batch 2 --seq 16 --normalized-dim 4096 --seed 123 --check-grad
# from a clean checkout; the output goes outside the tree so git_dirty stays false
python scripts/ws1_gdn_provider_agreement.py > "${TMPDIR:-/tmp}/gdn_provider_agreement.json"

• That is the local install. The cluster built the same extension in place with the same
  environment variables (python setup.py build_ext --inplace) and refused to run unless
  rl_engine._C loaded from the checkout under test.
• tests/test_rocm_aiter_api_contract.py is ignored because it fails to import on main
  (_AITER_FWD_REQUIRED_KEYWORDS is not defined); not ignoring it aborts collection.
• The check_ file imports real vLLM, and tests/test_framework_operator_integrations.py:69
  asserts "vllm" not in sys.modules, so it is named check_ (as tests/distributed/check_*.py)
  and runs only when named explicitly.
• check_operator flags above are the script's defaults (scripts/check_operator.py:107-120);
  the cluster ran it without them. These are regression checks on the norm operators from the
  PRs below; the C6 goldens are not registered (no gtest spec, no registry entry), so
  check_operator cannot run them. The check_ file uses H=16, HV=32, K=V=128, scale = K**-0.5.

Test results

Cluster B200 (sm_100), driver 580.126.20, torch 2.13.0+cu130, triton 3.7.1, vllm 0.30.0,
Python 3.12.14; extension built from source for sm_100 from a clean clone of 610f1b7. The
branch run was on a different node from the main baseline (details below).

check	main (32b765e)	this branch (610f1b7)
full suite	17 failed, 2942 passed, 923 skipped	18 failed, 3119 passed, 923 skipped: the same 2 fixed, 3 timeouts not on main (below)
tests/check_gdn_recurrent_golden.py	—	31 passed
tests/test_gdn_state_contract.py	—	19 passed
regression pytest (PRs below)	—	all pass (counts in details)
check_operator rms_norm / rms_norm_gated / qwen3_next_rms_norm	—	pass_rate=1.0000 each
runner at f8d9399, clean clone (git_dirty: false)	—	recurrent and conv sections identical to the earlier run at 1d69312; new conv_silu and conv_noact_bf16 sections (details)

Failure sets are compared by test ID against the main baseline; the two fixed are fixed at
the bottom of the stack. Arithmetic: 4060 collected (main 3882), and 2942 + 2 fixed + 178
newly collected − 3 = 3119. This PR adds 19 collected tests (tests/test_gdn_state_contract.py).

Three failures are not on main, all spawn timeouts (result_queue.get -> queue.Empty) in
multi-process TP2 tests of tests/test_vocab_parallel_logp.py:
TestCrossTPBitwise::test_tp2_bitwise_identical_to_tp1[even-bf16], [even-fp32] and
TestTritonNativeCrossTP::test_tp2_native_matches_tp1_and_repeat[bf16]. They did not
reproduce: on one node (1-minute load average about 8–20), main (32b765e, built in the
same run) and 610f1b7 alternated, five rounds each, over all six cases of those two test
classes; every case passed in every round on both sides, about 50–66 s per round on both.
This PR changes no logp or tensor-parallel code, though these tests import modules the stack
changes (the registry, gtest specs, ws1_workload, the rebuilt _C); the A/B above is what
speaks to that.

Earlier run, at 1d69312 (on the baseline's node): 17 failed, 3120 passed, 923 skipped, with
two different spawn timeouts not on main
(tests/test_linear_logp.py::test_native_tensor_parallel_matches_full_reference_cpu_gloo_4_ranks
and TestCrossTPBitwise::test_tp2_bitwise_identical_to_tp1[even-bf16]). Rerun on that node,
two of three runs passed; an A/B on one node, main and 1d69312 alternating five runs each,
passed both tests in all 10 runs.

Recurrent step vs the packed-decode provider (test_golden_matches_packed_decode_provider,
check_gdn_recurrent_golden.py:132-141; B ∈ {1, 4, 17, 64}, seed=batch, bf16 I/O,
use_qk_l2norm_in_kernel=True, random inputs). Bounds are regression bounds, not gate
evidence (:50-65); measured values from the runner:

state	asserted max|d out| / max|d state|	measured max|d out| over B	measured max|d state|	out elements differing (B=1/4/17/64)
fp32	≤ 1e-3 / ≤ 1e-5	1.49e-8 … 6.10e-5	≤ 2.98e-7	1 / 2 / 10 / 40
bf16	≤ 1e-3 / ≤ 5e-3	3.73e-9 … 3.05e-5	≤ 1.95e-3	2 / 2 / 14 / 36

Conv update vs causal_conv1d_update (:283-323; bias=True, silu, dim_first=True,
W=4, dim=8192, all rows active, one seed per batch): rolled state bitwise in all 8 cases.
Output elements differing: fp32 cache 0 / 0 / 1 / 5 (max 2.44e-4 at B=17, 3.91e-3 at B=64;
asserted ≤ 32 elements, max|diff| ≤ 1e-2); bf16 cache 0 / 0 / 0 / 3 (max 1.56e-2 at B=64;
asserted at B ∈ {1, 17}: ≤ 32 elements, max|diff| ≤ 7e-2). The fp32-cache mismatches come
from Triton's SiLU implementation, not from contraction or the convolution (Notes; measured
by the runner's conv_silu section at f8d9399).

Targeted tests and check_operator output (5e3630e)

tests/test_rms_norm.py                         57 passed, 72 skipped in 10.67s
tests/test_qwen3_next_norm.py                  141 passed in 9.33s
tests/test_qwen3_next_workload.py              7 passed in 4.00s
tests/test_ws1_gtest_gpu.py                    9 passed in 52.09s
tests/test_gdn_state_contract.py               19 passed in 5.79s
tests/test_vjp_fp32.py                         50 passed in 7.01s
rl_engine/tests/test_dispatch.py               17 passed in 6.20s
tests/check_qwen3_next_norm_providers.py       9 passed, 14 warnings in 117.07s (0:01:57)
tests/check_gdn_recurrent_golden.py            31 passed, 14 warnings in 70.04s (0:01:10)
rms_norm               suite=rms_norm passed=True pass_rate=1.0000
rms_norm_gated         suite=rms_norm_gated passed=True pass_rate=1.0000
qwen3_next_rms_norm    suite=qwen3_next_rms_norm passed=True pass_rate=1.0000

Failure IDs: main (32b765e) vs this branch (5e3630e), cluster

main (32b765e): 17 failed
  [fixed below] rl_engine/tests/test_dispatch.py::test_npu_registry_preserves_per_operator_cpu_fallbacks
  tests/distributed/test_rocm_attention_transport.py::test_rccl_adapter_world_sizes_match_the_shared_collective
  tests/test_attention_correctness.py::test_strict_rocm_aiter_ck_direct_decode_rejects_ignored_output
  tests/test_attention_correctness.py::test_strict_rocm_aiter_ck_direct_decode_uses_callers_output
  tests/test_attention_correctness.py::test_strict_rocm_aiter_ck_reuses_immutable_provenance_inputs
  tests/test_attention_dispatch.py::test_implementation_kind_policy_filters_without_marking_fallback
  tests/test_attention_dispatch.py::test_registered_backend_resolves_with_provenance
  tests/test_cross_config_cli.py::test_run_uses_only_cpu_and_resumes_when_cuda_is_available
  tests/test_cross_config_runner.py::test_cpu_smoke_cases_preserve_read_only_scoring_and_exact_provenance
  tests/test_cross_config_runner.py::test_runner_resumes_valid_attempt_and_retries_after_identity_or_tensor_change
  tests/test_distributed_grpo_loss.py::TestSingleRank::test_dispatch_resolves_this_backend
  tests/test_linear_logp.py::test_triton_det_tp_matches_single_rank_and_replicates[2]
  [fixed below] tests/test_rms_norm.py::test_registry_dispatches_rms_norm
  tests/test_rocm_logprob_backend.py::TestFusedKernelPath::test_tile_stats_read_input_dtype_exactly[triton]
  tests/test_swiglu.py::test_autograd_wrapper_contiguity_and_gradient_routing[True-needs_grad2]
  tests/test_ws1_candidate_evidence.py::test_ws1_cuda_and_triton_candidate_runtime_provenance
  tests/test_ws1_chain_integration.py::test_row_local_linear_vjp_matches_per_row_outer_and_gemv

this branch (5e3630e): 18 failed
  the 15 main failures not marked [fixed below], plus three spawn timeouts not on main:
  [timeout] tests/test_vocab_parallel_logp.py::TestCrossTPBitwise::test_tp2_bitwise_identical_to_tp1[even-bf16]
  [timeout] tests/test_vocab_parallel_logp.py::TestCrossTPBitwise::test_tp2_bitwise_identical_to_tp1[even-fp32]
  [timeout] tests/test_vocab_parallel_logp.py::TestTritonNativeCrossTP::test_tp2_native_matches_tp1_and_repeat[bf16]

Runner output at 36a5974 and run provenance (not reproducible from the branch)

• The runner run at f8d9399 built _C from its own clean clone of the ref and checked that
  both rl_engine.__file__ and rl_engine._C.__file__ were inside that clone. The runner,
  the goldens and the tests are unchanged after f8d9399 (610f1b7 touches only the design
  note; the gated branch's OptionalCUDAGuard fix, which came in by merge at the time, touches
  only csrc/cuda/rmsnorm.cu).
• It reported git_dirty: false. Its recurrent and conv sections are identical to the
  earlier run at 1d69312. Provenance records rl_engine_file (inside the clone) and env
  (FLA_USE_FAST_OPS and TRITON_DEFAULT_FP_FUSION, both unset).
• fusion_check: fusion_off_effective: true; it now covers every variant an arm compiles:
  all 12 fusion-off variants carry enable_fp_fusion=False, all 12 fusion-on variants True.
• conv_kernels (the SiLU specializations, 6 per arm): every variant has ex2.approx (2) and
  div.full.f32 (2) in its PTX, and SASS FFMA is 0 in all 12.
• conv_silu (x widened to fp32, fp32 cache and output; fusion on): pre-activation
  mismatches 0 at B = 1, 4, 17, 64. SiLU outputs differing: 3,060 / 8,192, 12,609 / 32,768,
  53,270 / 139,264 and 199,728 / 524,288; at B=64, 170,817 by 1 ULP, 23,201 by 2, 5,298 by
  3–4, 412 by more. Triton's x / (1 + tl.exp(-x)) on the golden's pre-activation values
  differs from the provider in 0 elements at every B; the variant with div_rn and
  libdevice.exp differs from the golden in 0; the two variants that swap only one of them
  match neither side.
• conv_noact_bf16 (activation off, fp32 cache): with fusion on, the bf16-output
  specialization's PTX has fma.rn.f32x2 (4) and its SASS FFMA (4); the fp32-output
  specialization has mul.f32x2 (4), no FFMA, and 0 mismatches. bf16 outputs differing:
  1 / 0 / 4 / 14 (max|diff| 3.91e-3 at B=64); 18 of the 19 have |out| < 0.11, and the largest
  gap in bf16 ULPs is 96, at |out| ≈ 2.4e-7. With fusion off: no FFMA, and 0 mismatches at
  every B.
• Device: NVIDIA B200, capability (10, 0); torch 2.13.0+cu130, triton 3.7.1, vllm 0.30.0,
  Python 3.12.14.

Earlier results, at the former merge commit 09b7aeb (pre re-stack), b8c6179, 78c5bca and cefa0d3

Cluster, same software as above; each run built _C from a clean snapshot of its ref and
refused to run unless rl_engine._C.__file__ was inside it.

• 09b7aeb (the former first merge of the gated branch, at 5eaeca8; this commit no longer exists on the linear branch, its tree equalled 7b30633 + the gated branch at 5eaeca8): full suite
  15 failed, 3117 passed, 923 skipped (4055 collected); no new failures against main, the
  same 2 fixed. It ran on a different B200 node from the baseline's.
  check_gdn_recurrent_golden.py 31 passed (incl. the provider null-block assert),
  test_gdn_state_contract.py 19, test_qwen3_next_norm.py 136, check_qwen3_next_norm_providers.py 9,
  test_qwen3_next_workload.py 7, test_dispatch.py 17, test_rms_norm.py 57 passed /
  72 skipped, test_ws1_gtest_gpu.py 9, test_vjp_fp32.py 50; check_operator ×3
  pass_rate=1.0000. Its runner (the version at 7b30633) gave recurrent and conv numbers
  identical to the run at 5216a6c.
• 5216a6c: the runner's recurrent and conv numbers that design note §4
  quotes (:134-147, :163-167). Its fusion-off arm did not take effect (the in-process knob
  reused the fused kernel); 10e5230 fixed that, so its FMA reading is not used.
• 2d895d0: the fixed runner. Fusion-off arm effective; mismatch counts and
  max|diff| identical with fusion on and off. This is the fusion A/B on the SiLU path (design
  note :189-191).

Local, 16204ab: 2× B200 (sm_100), driver 580.126.20, torch 2.13.0+cu130, triton 3.7.1,
vllm 0.30.0, transformers 5.17.0, flashinfer 0.6.18.post1, Python 3.12.14.

full suite, local main (32b765e): 19 failed, 2940 passed, 923 skipped
full suite, local cefa0d3:        17 failed, 3078 passed, 923 skipped   (no new failures)

Measured at 16204ab against main, on Python 3.10 with the hook versions pinned in
.pre-commit-config.yaml: real pre-commit, no new findings (commits through 7862a12
were also checked with the pinned hooks); mypy --ignore-missing-imports rl_engine/, no new
errors; mkdocs build --strict, 8 warnings, the same 8 as main.

Lint at the tip

At c0ab21c, the pinned pre-commit (Python 3.10) over every file the four stacked PRs
change against main (pre-commit run --from-ref 32b765e --to-ref HEAD, 36 files) has one
finding: black and flake8 on rl_engine/kernels/ops/pytorch/norm/rms_norm.py. That file
already fails both on main with the same hunks (four blank lines before the first
top-level function after strict_add_rms_norm, inline-comment spacing, one blank line
before class NativeRMSNormOp; flake8 E303 and E302). The stack adds no lint findings.
The commits after c0ab21c change scripts/ws1_gdn_provider_agreement.py, the design
note and, through the gated merge, csrc/cuda/rmsnorm.cu; at 610f1b7 the runner passes
black, isort and flake8 with the pinned settings, and the design note has no trailing
whitespace and ends in a newline.
At 610f1b7: mkdocs build --strict gives the same 8 warnings as main (the identical
set); mypy --ignore-missing-imports rl_engine/ (mypy 2.3.1, Python 3.10, as ci.yml
runs it) gives 56 errors in 16 files on both main and 610f1b7, the same messages apart
from line numbers. The stack adds no lint, docs or type findings.

Notes

Which provider this aligns to, and the mixed-step caveat

• A decode-only batch with no speculative decoding returns early into
  _forward_core_decode_non_spec (qwen_gdn_linear_attn.py:1295-1307) because
  VLLM_ENABLE_FLA_PACKED_RECURRENT_DECODE defaults to on (envs.py:1199-1200).
  tests/check_qwen3_next_norm_providers.py asserts that default; it does not assert which
  kernel actually runs.
• VLLM_GDN_DECODE_KERNEL defaults to "cuda", but qwen3_next.py:495 constructs the layer
  with gqa_interleaved_layout=True, which makes _fused_gdn_decode_unsupported_reason
  (qwen_gdn_linear_attn.py:535-554) return a reason. The layer logs a fallback to
  "triton" (:520-523), or raises ValueError if VLLM_GDN_DECODE_KERNEL was explicitly
  set to cuda (:516-519). The fallback was observed in a real engine (B200, TP1 and TP4,
  real checkpoint, enforce_eager, not strict): the startup log shows Falling back to the Triton GDN decode path and GDN decode kernel: triton. That log is not part of this PR.
• The packed kernel is the provider only for decode-only steps. When the step also holds
  a prefill, _forward_core routes the cached decode rows through causal_conv1d_fn (branch
  at qwen_gdn_linear_attn.py:1373, call at :1378-1388) and
  fused_sigmoid_gating_delta_rule_update (split_non_spec at :1408-1412, branch at
  :1493, call at :1497-1512). So this golden matches what rollout runs in decode-only
  steps, not in steps shared with a prefill.
• Under MTP, the packed kernel is not used in steps that carry draft tokens (see "Deliberately
  not in this PR").

Not reproducible from this branch: the mixed decode+prefill measurement

This measurement is not in this PR and has not been published; treat it as a reported
observation until the check that produced it is submitted. Design note §5 labels it the same
way (:225-227). It drove the real GDNAttentionMetadataBuilder.build() and _forward_core
of one standalone layer built from the checkpoint's config.json, on B200. Limits:
parameters and cache were synthetic (no weights loaded); single process, no engine, scheduler
or CUDA graph; the test, not the scheduler, built the attention metadata (decode rows first).

For one target decode request with an fp32 recurrent state, three prefill-bearing step
compositions gave identical numbers. The convolution still matched bitwise; the two
recurrent kernels did not:

head counts	step's bf16 output	fp32 state
TP1 (H=16, HV=32)	matched	75,146 of 524,288 elements differ (8.8e-08 relative)
TP4 per-rank (H=4, HV=8)	1 element differs (4.8e-05 relative)	32,663 of 131,072 differ (1.7e-07)

At TP1 the difference reached a bf16 output within the next 16 plain decode steps in 4 of 20
seeds. With synthetic parameters that frequency does not carry over to real weights; it shows
only that the difference propagates. At TP4 per-rank head counts it shows up in the same
step's output. This is a provider-side batch-composition dependence, outside what this golden
can fix. Whether the golden's target is right in every step depends on the upstream fix:

• [Model] Enable batch-invariant mixed decode and prefill for Qwen GDN vllm-project/vllm#49827 (open, not merged) routes mixed-step recurrent decodes
  through the packed kernel too. Its two commits, applied to 0.30.0, gave a gap of 0 at both
  head counts above; its scheduler part was not tested. It does not change the mixed-step conv
  path (causal_conv1d_fn). Its own validation is on Qwen3.5 (non-interleaved), H100, TP1.
• Disabling VLLM_ENABLE_FLA_PACKED_RECURRENT_DECODE sends every non-speculative step
  through fused_sigmoid_gating_delta_rule_update. In that configuration the measurement
  found the decode row's output and state bitwise equal across step compositions
  (prefill-target rows still differ, a FlashInfer CP issue). This golden's target would then
  have to change, or a second golden targeting that kernel would be needed.

How the golden relates to the kernel, and where it is not a transcription

1. Gating is fused, in fp32: beta = sigmoid(b), g = -exp(A_log) * softplus(a + dt_bias),
   with the kernel's threshold branch at 20. HF computes these as separate PyTorch ops.
2. No repeat_interleave: i_h = i_hv // (HV // H), so q/k stay at 16 heads while v has 32.
3. QK norm is x / sqrt(sum(x*x) + 1e-6): not an RMSNorm, not F.normalize. scale is
   applied to q after the norm, and k is never scaled.

Not a transcription:

• softplus: the kernel computes tl.log(1.0 + tl.exp(x)) (fused_recurrent.py:327); the
  golden computes torch.log1p(torch.exp(safe)), where safe is x on the taken branch
  (gated_delta_rule.py:114-116). These round differently.
• The kernel's exp/log become fast_expf/fast_logf when FLA_USE_FAST_OPS=1
  (third_party/flash_linear_attention/ops/op.py:16-25). The goldens model the default.
• Contractions use the repo's 32-wide chunked sum (_chunked_sum, gated_delta_rule.py:76-94)
  rather than the kernel's tree reduction. It fixes the reduction shape per row regardless
  of batch size, which is the argument for L1; L1 itself is established empirically
  (test_golden_is_batch_invariant, check_gdn_recurrent_golden.py:162-188). The same choice
  is why the golden is not bitwise against the kernel. For a last dimension that is not a
  multiple of 32, _chunked_sum zero-pads to the next chunk boundary (:86-91, since 0b41350;
  before that it fell back to a plain .sum); this does not trigger at K=V=128.
• The test feeds raw randn q/k (check_gdn_recurrent_golden.py:85) with
  use_qk_l2norm_in_kernel=True (:110), so the kernel normalises them, as vLLM's decode path
  calls the provider (qwen_gdn_linear_attn.py:1707). The golden's use_qk_l2norm=False mode
  (prefill's convention) is checked only for producing a different result (:405-427); it is
  not compared against a provider.

State ABI: index validation and the two NULL_BLOCK_ID contracts

vLLM's causal_conv1d_update does not check index values even with validate_data=True;
that flag adds only shape and stride asserts and a null_block_id is not None assert (vLLM
causal_conv1d.py:1151-1153, 1188-1201). An out-of-range index there is an unchecked memory
access. This is read from the source, not exercised.

	recurrent provider	conv provider	both goldens
which indices skip	<= 0 (fused_recurrent.py:300)	== null_block_id only, default NULL_BLOCK_ID = 0 (vLLM causal_conv1d.py:835; v1/attention/backends/utils.py:47)	<= 0
output for a skipped row	zeros (fused_recurrent.py:301-302)	not written (vLLM causal_conv1d.py:835-839 returns before any store)	zeros
state block	not touched (returns before any store)	not touched	not touched

Asserted for the recurrent pair (check_gdn_recurrent_golden.py:152-156): both outputs are
zeros, and both the golden and the provider leave block 0 untouched. For conv, only the golden
is tested (:326-336). The golden treats negative conv indices as inactive
(tests/test_gdn_state_contract.py:54-59), whereas the provider would treat them as real
indices. The design note states the two contracts separately (:100-110).

The conv half: coverage and the two mismatch mechanisms

Product rounding is pinned by test_conv_bf16_products_round_before_fp32_accumulation (CPU)
and by test_conv_provider_preserves_bf16_product_cancellation, which checks that the
provider and the golden agree on an input whose exact product would not cancel.

what	where asserted	bound
rolled conv state	B ∈ {1, 4, 17, 64} × cache ∈ {fp32, bf16}	torch.equal (8 cases)
output, fp32 cache	B ∈ {1, 4, 17, 64}	≤ 32 elements differ in bits, max|diff| ≤ 1e-2
output, bf16 cache	B ∈ {1, 17}	≤ 32 elements differ, max|diff| ≤ 7e-2

The test docstring (:301-302) quotes the measured fp32 counts; they are measured, not
asserted.

With an fp32 cache the output is not bitwise. The cause depends on the Triton
specialization, and both mechanisms are on the provider side. Measured by
scripts/ws1_gdn_provider_agreement.py (conv_silu, conv_noact_bf16) on B200 at f8d9399
(design note :169-205).

• With SiLU (Qwen3-Next's configuration and the check file's): the activation.
  • With the activation off and fp32 output, provider and golden agree bitwise at every
    batch size tested, so the convolution itself matches.
  • Triton lowers acc / (1 + tl.exp(-acc)) (vLLM causal_conv1d.py:1085) to ex2.approx
    and div.full.f32. Applying that expression to the golden's pre-activation values
    reproduces the provider bitwise, and the golden equals libdevice.exp with IEEE
    division. Swapping only one of the two reproduces neither side.
  • About 38% of fp32 outputs differ, mostly by 1 ULP. Only values straddling a bf16
    rounding midpoint survive the store: 0 / 0 / 1 / 5, one bf16 ULP each.
  • No contraction is involved: there is no FFMA in these specializations, and
    TRITON_DEFAULT_FP_FUSION=0 changes nothing.
• Without an activation and with bf16 output: FP contraction.
  • This specialization contracts the tap multiply-adds (fma.rn.f32x2 / FFMA); its
    fp32-output twin does not, and matches bitwise.
  • 1 / 0 / 4 / 14 outputs differ (max|diff| 3.9e-3), mostly near-cancelling ones, where the
    gap reaches up to 96 bf16 ULPs; the count drops to 0 with TRITON_DEFAULT_FP_FUSION=0.
  • Qwen3-Next's decode path does not use this specialization.
• Open: the recurrent provider computes exp(g) and sigmoid(b) with Triton, and the
  golden with PyTorch; the same kind of difference may account for part of the recurrent
  output mismatches. Not investigated (design note :207-210).

Production does not use a conv bias. Qwen3-Next's conv1d is built with bias=False
(qwen_gdn_linear_attn.py:418-421). The only provider comparison without a bias is the single
hand-built cancellation input (check_gdn_recurrent_golden.py:465-475, activation=None).
bias=None with random inputs is never compared against the provider. dim_first=False is
compared only golden against golden (:430-448).

L1, and the bf16 recurrent state

test_golden_is_batch_invariant (check_gdn_recurrent_golden.py:162-188) runs one batch of
64 (seed 3, all rows active) for both state dtypes and checks that rows 0, 1, 31 and 63 produce
bitwise the same output and state block when run alone. This compares the golden against
itself. No L1 claim is made for the provider; the mixed-step observation above reports a
counterexample for vLLM 0.30.0 (mixed decode+prefill steps, standalone layer, synthetic
parameters).

The strict profile uses an fp32 recurrent state; bf16 is a differential experiment (design
note :262-263). test_bf16_state_rounding_stays_within_fixed_fixture_bound (:194-225) runs
the golden against itself (fp32-state run vs bf16-state run), with no provider. The gate
inputs a/b/A_log/dt_bias are fixed for all 128 steps; only the token changes. One fixed
fixture: B=8, 128 steps, seed 11. It asserts a nonzero first-step drift, max relative state
drift < 0.05, and that the second half is no more than 2× the first half plus 1e-3. It is a
regression bound for that fixture, not evidence of a general plateau, of prefill/decode
equality, or of any bound on model logits. Earlier 1024-step and prefill-vs-decode tables were
withdrawn in dbb8d00 because they had no checked-in runner (:25-28, design note :214-217).

Deliberately not in this PR

Adapted from the design note §6; the MTP and backward reasons are restated against RFC #428:

deferred	why
Speculative decode / MTP	RFC §2.2 excludes speculative decoding from the first claim. Qwen3-Next ships its MTP head in the checkpoint (mtp.*, loaded by model_executor/models/qwen3_next_mtp.py), not a separate draft model, and the head itself is full-attention (qwen3_next_mtp.py:90-92). In steps that carry draft tokens, enabling it changes the target model's GDN path (a step with zero draft tokens drops spec_sequence_masks, v1/attention/backends/gdn_attn.py:236-243, and plain decodes stay on the packed kernel). Verification steps go through causal_conv1d_update + fused_sigmoid_gating_delta_rule_update with num_accepted_tokens, never the packed decode kernel this golden targets. Plain decodes in such a step are reclassified as prefills (gdn_attn.py:283-289). The fused fused_gdn_decode_post_conv_mtp kernel is unreachable for Qwen3-Next (qwen_gdn_linear_attn.py:1834 needs gdn_decode_kernel == "cuda"). Read from the source, not measured.
Backward	RFC §2.2 item 4: backward need not match rollout, only be correct for the replayed forward. RFC §9.1 makes it a separate work item, RFC #428 C7 (GDN backward/recompute adapter). supports_backward=false here. (dcb9263 only stops autograd through the golden's torch.where from producing NaN; it adds no backward claim.)
Provider bridge / registry entry	should wait until the golden has survived a drift sweep against a real checkpoint
Paged block allocation policy	the ABI is mirrored; the allocator is not modelled
TP sharding of A_log / dt_bias	single card only
ROCm / Ascend	CUDA first, per the WS1 order

Also not covered: the prefill side. vLLM's bundled FLA chunked kernel rejects fp32 q/k/v
(third_party/flash_linear_attention/ops/chunk.py:213). On SM100 with head_k_dim=128 and a
CUDA ≥ 13 runtime, though, _resolve_gdn_prefill_backend selects FlashInfer by default
(qwen_gdn_linear_attn.py:129-147), so that assert is not on the default prefill path on this
hardware. FlashInfer's SM100 prefill paths reject fp32 q/k/v as well: the non-CP path via
_cutlass_io_dtype (flashinfer/gdn_kernels/blackwell/gdn_prefill.py:66-74) and the CP path
(gdn_cp_prefill.py:736-738); that is from reading flashinfer 0.6.18.post1, not from a run. An
fp32 q/k/v prefill is therefore unavailable on either default backend. The opt-in CuteDSL
backend (qwen_gdn_linear_attn.py:108, :137, :148) was not checked.

Design note corrections in this branch

• 7b30633: decode-kernel selection under gqa_interleaved_layout (§1); the actual MTP path;
  separate conv and recurrent NULL_BLOCK_ID contracts (§3); softplus not being a
  transcription (§2); validate_data not checking index values.
• 2d895d0: measured agreement tables from the runner (§4).
• 52f7f61: the FP-contraction result (replaced in 610f1b7).
• 7862a12: the mixed-step caveat scoped to what was measured (§5).
• 1d69312: renamed to docs/design/rfc428-c6-gdn-recurrent-replay.md and retitled "RFC [RFC][Qwen3-Next-80B-A3B-Instruct][CUDA/ROCm] VIME/vLLM operator-level train-rollout consistency roadmap, ablation matrix, and integration plan #428
  C6", backward written "RFC [RFC][Qwen3-Next-80B-A3B-Instruct][CUDA/ROCm] VIME/vLLM operator-level train-rollout consistency roadmap, ablation matrix, and integration plan #428 C7", so neither collides with upstream's WS1 C6 ([WS1 Closeout][KV] Direct decode-prefill consistency sweep #272) / C7
  ([WS1 Closeout][KV] Stateful cache path and generate-rescore consistency #273); the §5 mixed-step numbers and the §7 startup failure labelled as reported
  observations, not acceptance evidence; every bound labelled a regression bound, with the
  contract's forward_accuracy/by_op_class/reduction row for scale (§4, :122-127).
• 610f1b7: the two conv mismatch mechanisms, measured by the runner at f8d9399, and the
  recurrent provider's Triton exp/sigmoid as an open item (§4, :169-210).

What CI will and will not run

As of 2026-10-01 no CI path is known to execute these tests, before or after merge.

• On main (32b765e and the current 1968a87), CI-Pipeline's linting fails at
  Run pre-commit hooks, so unit-tests is skipped. Docs fails at both commits too.
• WS1-chain-GPU and ws1-gtest-gpu stop at Configure runpodctl. The cause is step order:
  runpodctl config --apiKey, run as the first runpodctl call on a fresh runner, finds no
  config file (run 36835086246 logs 'runpodctl config' is deprecated then
  error saving config, reproduced locally with v2.14.0 on an empty HOME). ws1-gtest-gpu
  has never succeeded: as of 2026-10-01, 122 runs (69 failed, 40 skipped, 13
  action_required), and its first run (2026-08-19) already failed at this step. A separate
  fix is being prepared.
• gpu-ci (pull_request_target only, gpu-ci.yml:4; label needs-gpu-ci) uses the same
  command (:50) but runs runpodctl version first, which creates the config file, so it got
  past setup on its last run that reached RunPod (2026-09-11, run 34585491929) and then failed
  at pod create. No run since. Its pytest tests/ (ci/run_gpu_ci.sh:133) would also stop at
  the aiter collection error.
• ws1-chain-npu was queued on 1968a87 and cancelled on 32b765e.

If those are fixed, the workflows' scripts would do this with this branch:

1. ci.yml (needs: linting; push and PR to main/test): unit-tests now runs
   tests/test_gdn_state_contract.py on a CPU runner (ci.yml:70), not the check_ file.
2. ws1-gtest-gpu.yml: unchanged by this branch. The goldens fall under its
   rl_engine/kernels/ops/** path, so it triggers for same-repo PRs and on push to main;
   fork PRs skip it (:59). Its script ci/run_ws1_gtest.sh runs neither GDN file.
3. qwen3-next-provider-gpu.yml (new): runs both check_ files (:82) after checking the
   runtime versions and that rl_engine._C loaded from $GITHUB_WORKSPACE (:55-79). It runs
   on same-repo PRs to main (paths :20-25) and on workflow_dispatch, not on push; fork PRs
   get only a notice job (:36-45). It needs a self-hosted runner labelled
   rl-kernel-qwen3-next (:49); whether upstream has one has not been confirmed.
4. gpu-ci.yml: ci/run_gpu_ci.sh runs pytest tests/, which collects
   test_gdn_state_contract.py but not the check_ file. The check_ file would also skip
   there: the script builds on a runpod/pytorch:2.4.0 image with torch 2.4.1 and never
   installs vLLM (run_gpu_ci.sh:19, :193-200).
5. ws1-chain-gpu.yml: push and PR to main/test, no paths filter, skipped for fork
   PRs (:46). Its chain (ci/run_ws1_chain_gate.sh) instantiates each profile's declared
   candidate class by path, not through the registry (rl_engine/alignment/qwen3_dense.py:374-396;
   RMSNormCudaOp for rms_norm); none of this layer's own files are on that path;
   RMSNormCudaOp itself is changed by the PRs below.

Hardware, base and stacking

• sm_100 (Blackwell), not the sm_90 the project's benchmarks usually use. Per RFC §2.2 no claim
  is made across H100/B200.
• Stacked on feat/cuda-qwen3-next-gated-rmsnorm ([WS1][CUDA][Qwen3-Next] Gated RMSNorm CUDA kernel for the GDN block (RFC #428 stack 3/4) #468, cf68fd9), which is on
  feat/cuda-qwen3-next-c1-norm ([WS1][CUDA][Qwen3-Next] C1: zero-centred RMSNorm references and CUDA kernel (RFC #428 stack 2/4) #467) and fix/registry-cuda-rmsnorm-dispatch ([WS1][CUDA][Qwen3-Next] Restore CUDA dispatch for rms_norm (RFC #428 stack 1/4) #466); all three
  must merge first, and this branch contains their commits. Linear since 2026-10-04 (see Latest
  Status); 395fef8 merges cleanly into the current upstream/test-qwennext (11cac8c,
  git merge-tree --write-tree).

Known review items left as they are

• F5, no operator page. There is no docs/operators/ page for the two goldens; the design
  note docs/design/rfc428-c6-gdn-recurrent-replay.md is the only documentation.
• F15, private imports. The runner loads the check_ file and calls its underscore-private
  helpers and _RECURRENT_BOUNDS (scripts/ws1_gdn_provider_agreement.py:147-181, :267-273, :356-359).
• F16, duplicated chunked sum. _chunked_sum (gated_delta_rule.py:76-94) re-implements
  the fixed 32-wide chunking of shape_invariant_rstd (rl_engine/kernels/ops/pytorch/norm/rms_norm.py:100)
  rather than sharing it.
• F18, function-local imports, e.g. CausalConv1dUpdateOp imported inside test functions
  (check_gdn_recurrent_golden.py:260, :327, :340, :432, :452).
• F19, history in docstrings and the note, e.g. the withdrawn tables
  (check_gdn_recurrent_golden.py:25-28) and "an earlier version of this note" (design note
  :149-151).

None of these changes behavior. They are left for follow-ups; this is the top of the stack, so
a follow-up PR is the natural place.

Summary by CodeRabbit

• New Features

  • Added Qwen3-Next zero-centred and gated RMSNorm operators, with PyTorch and CUDA implementations and support for SiLU or sigmoid gating.
  • Added PyTorch reference operations for Gated DeltaNet recurrent steps and causal convolution updates.
  • Added operator guides, workload validation, and performance and accuracy reports for Qwen3-Next normalization.

• Bug Fixes

  • Improved RMSNorm input validation and CUDA dispatch fallback when required GPU support is unavailable.
  • Preserved inactive cache entries and returned zero outputs for inactive or empty batches.

• Tests

  • Expanded CPU and GPU checks for normalization, recurrent-state behavior, provider agreement, and batch invariance.

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Reviewing files that changed from the base of the PR and between 62b481b and c214004.

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⛔ Files ignored due to path filters (3)

• docs/usage/evidence/qwen3-next-rms-norm-b200/figure.png is excluded by !**/*.png
• docs/usage/evidence/qwen3-next-rms-norm-gated-b200/figure-gated_rmsnorm.png is excluded by !**/*.png
• docs/usage/evidence/qwen3-next-rms-norm-gated-b200/figure-zero_centred_rmsnorm.png is excluded by !**/*.png

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📒 Files selected for processing (18)

• .github/workflows/ws1-gtest-gpu.yml
• ci/run_ws1_gtest.sh
• csrc/cuda/rmsnorm.cu
• csrc/ops.cpp
• docs/operators/qwen3-next-rms-norm-gated.md
• docs/operators/qwen3-next-rms-norm.md
• docs/usage/evidence/qwen3-next-rms-norm-b200/report.json
• docs/usage/evidence/qwen3-next-rms-norm-gated-b200/report.json
• rl_engine/_C.pyi
• rl_engine/kernels/ops/cuda/norm/rmsnorm.py
• rl_engine/kernels/ops/pytorch/linear_attn/gated_delta_rule.py
• rl_engine/kernels/registry.py
• scripts/plot_qwen3_next_norm_evidence.py
• scripts/qwen3_next_norm_evidence.py
• tests/check_gdn_recurrent_golden.py
• tests/test_gdn_state_contract.py
• tests/test_qwen3_next_norm.py
• tests/test_rms_norm.py

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🚧 Files skipped from review as they are similar to previous changes (1)

• docs/operators/qwen3-next-rms-norm-gated.md

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📝 Walkthrough

📝 Walkthrough

Walkthrough

This change adds Qwen3-Next zero-centred and gated RMSNorm operators for PyTorch and CUDA. It adds workload validation, dispatch support, tests, CI checks, and operator documentation. It also adds PyTorch references for GDN recurrent and convolution steps, with provider checks and replay documentation.

Changes

Qwen3-Next normalization

Layer / File(s)	Summary
CUDA kernels and bindings csrc/cuda/rmsnorm.cu, csrc/ops.cpp, rl_engine/_C.pyi	RMSNorm forward and input-gradient APIs accept a weight offset. The CUDA implementation adds gated RMSNorm operations, validation, and launch checks. The bindings declare API version 2.
Python operators and dispatch rl_engine/kernels/ops/cuda/norm/rmsnorm.py, rl_engine/kernels/ops/pytorch/norm/*, rl_engine/kernels/registry.py, rl_engine/tests/test_dispatch.py, rl_engine/tests/test_rms_norm.py	Python operators add zero-centred and gated RMSNorm variants. Dispatch tests cover CUDA priority, PyTorch fallback, and extension API compatibility.
Norm workload and invariance harness rl_engine/kernels/gtest/*, rl_engine/testing/qwen3_next_*, rl_engine/testing/ws1_workload.py, scripts/check_*_invariance.py, tests/test_qwen3_next_workload.py, tests/test_ws1_ascend_closeout.py, tests/test_ws1_gtest_gpu.py, ci/run_ws1_gtest.sh	The Qwen3-Next manifest defines norm operators, dimensions, fixtures, and backend profiles. Model-scoped adapters and invariance scripts use the manifest; tests cover validation and adapter selection.
Verification and operator documentation tests/test_qwen3_next_norm.py, tests/check_qwen3_next_norm_providers.py, .github/workflows/ci.yml, .github/workflows/qwen3-next-provider-gpu.yml, .github/workflows/ws1-gtest-gpu.yml, docs/operators/*, docs/.nav.yml, docs/usage/evidence/*, scripts/qwen3_next_norm_evidence.py, scripts/plot_qwen3_next_norm_evidence.py	Tests cover RMSNorm arithmetic, gradients, invariance, and provider comparisons. CI workflows run selected checks. Operator documentation, evidence reports, and scripts record and plot measurements.

GDN reference operations and provider analysis

Layer / File(s)	Summary
Paged-state reference operators and contracts rl_engine/kernels/ops/pytorch/linear_attn/*, tests/test_gdn_state_contract.py	PyTorch reference operators implement recurrent and causal-convolution steps over paged state. Tests cover index validation, inactive rows, state preservation, and arithmetic behavior.
Golden checks and provider measurements tests/check_gdn_recurrent_golden.py, scripts/ws1_gdn_provider_agreement.py	Golden checks compare recurrent and convolution outputs and state with providers. The measurement runner reports batch comparisons, kernel details, and fusion-off results.
Provider replay design and workflow docs/design/rfc428-c6-gdn-recurrent-replay.md, .github/workflows/qwen3-next-provider-gpu.yml	The RFC documents provider paths, arithmetic and state contracts, measurements, and replay boundaries. The GPU workflow runs targeted provider checks.

Priority: ➖ Normal

Estimated code review effort: 5 (Critical) | ~120 minutes

Change: Feature

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Merge Risk: ⚪ Minimal · up to c2140

The previously identified reduction issue is fixed at the reviewed head. No actionable issue remains before normal merge checks.

Security Architecture Review

Security architecture risk: 🔵 Low · up to c2140

The inspected paths retain input validation and avoid mutating caller-owned reference state. No new privilege or isolation bypass was demonstrated, but compatibility across mixed builds and production state recovery remain only partially established.

Retained concerns
No architecture-level concerns identified.

Security review details

Security Blast Radius

• inferred — The inspected native entrypoints require an in-process caller supplying CUDA tensors. Their execution scope is the loaded extension process and the input tensor's device and current stream. The examined path does not establish remote, cross-tenant, or privileged-service reachability.

Trust Boundaries and Controls

• observed — Public normalization bindings validate CUDA residency, contiguity, supported dtypes, dimensions, and device agreement before internal launches. Gated inputs must match the input shape and dtype, activation selectors are restricted, and backward inputs receive consistency checks. These native controls remain applicable even when Python assertions are disabled.

Resilience and Maintainability Implications

• inferred — Out-of-place updates contain per-call computation failures by leaving input state unchanged. They do not enforce cross-call block ownership, serialize concurrent updates, or atomically publish recurrent and convolution results together. Production interruption, retry, rollback, and recovery guarantees remain outside the evidenced reference integration.

Hardening Proposals

• proposed — Consider applying explicit API-version compatibility checks to gated construction and dispatch as well as symbol checks, preventing future mixed-build control drift. No incompatible gated build was demonstrated in this review.
• proposed — Before adding a production provider bridge, define provider-specific sentinel validation, request-to-block authority, serialized state publication, and interruption recovery. Do not treat successful reference execution as validation of raw-provider metadata or combined state commits.

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Pre-merge checks | 3 | 2

❌ Failed checks (2 warnings)

Check name	Status	Explanation	Resolution
Linked Issues check		Issue #49827 requires coding changes for three boundaries: packed recurrent decode for cached rows in mixed decode/prefill steps, fixed FlashInfer prefill selection under batch-invariant mode, and 64-…	Implement the Qwen-specific batch-invariant path from #49827. Route cached rows through packed recurrent decode in mixed steps. Select the fixed FlashInfer prefill implementation under batch-invariant mode. Align non-final chunked-prefill c…
Docstring Coverage		Docstring coverage is 36.64% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 262 functions across 30 files. (5 skipped…	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (3 passed)

Check name	Status	Explanation
Out of Scope Changes check		The PR-owned changes remain related to GDN decode-step validation: PyTorch recurrent and convolution goldens, cache-state contract tests, provider comparison checks, CI wiring, and the C6 design note.…
Description Check		Check skipped - CodeRabbit’s high-level summary is enabled.
Title check		The title clearly identifies the PR's primary objective: adding Qwen3-Next GDN decode-step goldens and recurrent/convolution state-contract coverage.

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Full details: Linked Issues check

Explanation

Issue #49827 requires coding changes for three boundaries: packed recurrent decode for cached rows in mixed decode/prefill steps, fixed FlashInfer prefill selection under batch-invariant mode, and 64-token scheduler chunk alignment. This PR adds PyTorch GDN goldens, decode-only provider checks, state-contract tests, and documentation. The current description explicitly excludes mixed-step routing, prefill, and scheduler changes. The required #49827 implementation and its mixed-step, prefill, chunk-boundary, and online regressions are not present.

Resolution

Implement the Qwen-specific batch-invariant path from #49827. Route cached rows through packed recurrent decode in mixed steps. Select the fixed FlashInfer prefill implementation under batch-invariant mode. Align non-final chunked-prefill calls to the 64-token grid. Add the required boundary and online regressions.

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Full details: Docstring Coverage

Explanation

Docstring coverage is 36.64% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 262 functions across 30 files. (5 skipped: 5 unsupported.)

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Review comments at
@rl_engine/kernels/ops/pytorch/linear_attn/gated_delta_rule.py:
- Around line 76-90: Update _chunked_sum so non-multiple-of-32 widths use the
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📒 Files selected for processing (36)

• .github/workflows/ci.yml
• .github/workflows/qwen3-next-provider-gpu.yml
• ci/run_ws1_gtest.sh
• csrc/cuda/rmsnorm.cu
• csrc/ops.cpp
• docs/.nav.yml
• docs/design/rfc428-c6-gdn-recurrent-replay.md
• docs/operators/README.md
• docs/operators/qwen3-next-rms-norm-gated.md
• docs/operators/qwen3-next-rms-norm.md
• rl_engine/_C.pyi
• rl_engine/kernels/gtest/gradient_adapters.py
• rl_engine/kernels/gtest/operator_inputs.py
• rl_engine/kernels/gtest/operator_specs.py
• rl_engine/kernels/ops/cuda/norm/rmsnorm.py
• rl_engine/kernels/ops/pytorch/linear_attn/__init__.py
• rl_engine/kernels/ops/pytorch/linear_attn/causal_conv1d.py
• rl_engine/kernels/ops/pytorch/linear_attn/gated_delta_rule.py
• rl_engine/kernels/ops/pytorch/norm/qwen3_next_rms_norm.py
• rl_engine/kernels/ops/pytorch/norm/rms_norm.py
• rl_engine/kernels/registry.py
• rl_engine/testing/qwen3_next_norm_manifest.json
• rl_engine/testing/qwen3_next_workload.py
• rl_engine/testing/ws1_workload.py
• rl_engine/tests/test_dispatch.py
• scripts/check_forward_invariance.py
• scripts/check_gradient_invariance.py
• scripts/ws1_gdn_provider_agreement.py
• tests/check_gdn_recurrent_golden.py
• tests/check_qwen3_next_norm_providers.py
• tests/test_gdn_state_contract.py
• tests/test_qwen3_next_norm.py
• tests/test_qwen3_next_workload.py
• tests/test_rms_norm.py
• tests/test_ws1_ascend_closeout.py
• tests/test_ws1_gtest_gpu.py

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