[WS1][CUDA][Qwen3-Next] Gated RMSNorm CUDA kernel for the GDN block (RFC #428 stack 3/4)

[fusheng-ji]

Repository refactor update

Merged RL-Align/RL-Kernel:test-qwennext at a5a92ecf6cbf29fdcfc862846e53db5fa244c35e as requested in RFC #428. This PR still targets test-qwennext.

Implementation changes now live in the canonical rl_engine/backends, rl_engine/reference, rl_engine/runtime, and rl_engine/validation directories. Where present, model assembly and vLLM training bridges use rl_engine/models/qwen3_next and rl_engine/integrations/engines/train/vllm, respectively. Tests use tests/models/qwen3_next; evidence and validation commands use tools/validation/models and tools/validation/operators. Existing upstream compatibility entry points and pinned operator identifiers are preserved. CI commands and path filters follow the new layout, including the test-qwennext target.

Validation after migration: 295 passed, 72 skipped in the relevant regression suites. CUDA tests used extensions built from the matching migrated native sources on B200. Syntax, undefined-name/duplicate-import checks, formatting, and git diff --check passed.

Status [2026-10-08]

• Added: existing-implementation comparison, committed (scripts/qwen3_next_norm_reuse_check.py; report and figure in docs/usage/evidence/qwen3-next-norm-reuse-b200). Since b4bb977 the branch gained only that script, its evidence, the C3/C4 gate results for [WS1][CUDA][Qwen3-Next] C1: zero-centred RMSNorm references and CUDA kernel (RFC #428 stack 2/4) #467's op, and the merge of [WS1][CUDA][Qwen3-Next] C1: zero-centred RMSNorm references and CUDA kernel (RFC #428 stack 2/4) #467 (no change outside docs/ and that script). See Prior art.
• Since tip cf68fd9 named in the Latest Status below, the branch merged the updated [WS1][CUDA][Qwen3-Next] C1: zero-centred RMSNorm references and CUDA kernel (RFC #428 stack 2/4) #467 base (8ce67e0) and, on 2026-10-08, [WS1][CUDA][Qwen3-Next] C1: zero-centred RMSNorm references and CUDA kernel (RFC #428 stack 2/4) #467's latest state (1edc9d4, with bec7e7a). That merge resolved a conflict in rmsnorm.py: the plain op uses [WS1][CUDA][Qwen3-Next] C1: zero-centred RMSNorm references and CUDA kernel (RFC #428 stack 2/4) #467's API-version check _require_cuda_rmsnorm, and the gated op keeps the generic _require_cuda_symbols, since the gated bindings did not change signature. At 1edc9d4 with two B200s: the norm suites 263 passed (72 skipped, all Ascend), tests/check_qwen3_next_norm_providers.py 9 passed, and the four Qwen3-Next C3/C4 gates pass. The older results under Test results predate these merges.
• Added: comparison charts against transformers and vLLM (a441ff9 runner, 024823d evidence); see Comparison charts below.
• Known cost: the CUDA backward is about 75× slower than transformers at 262144 rows, for the same reason as [WS1][CUDA][Qwen3-Next] C1: zero-centred RMSNorm references and CUDA kernel (RFC #428 stack 2/4) #467: a serial ascending dweight fold that meets the singleton-aggregate check bitwise. FLA's rmsnorm_fn passes the same gate without one (see Prior art).

Latest Status [2026-10-04]

2026-10-04, later: re-stacked onto #467 (d03c852, on #466 6a4f078). #466 now adds the device guard a
maintainer asked for in the four plain CUDA RMSNorm launchers; this branch had added the same guards itself
(the commits now 263e4cf and 7f4012c), so after the replay those two commits keep only what #466 does
not have: the T == 0 early returns, the kernel launch checks, and the guards on the two gated launchers.
The tree differs from the previous tip only by #466's two comment lines and its two-device test. Commit
ids below are the replayed ones.

Ready for review. Third of a four-PR stack for #428, on top of
feat/cuda-qwen3-next-c1-norm (#467, tip d03c852), which is itself on
fix/registry-cuda-rmsnorm-dispatch (#466). Both must merge first. Tip cf68fd9.

2026-10-04: the maintainers retargeted the stack to test-qwennext and asked for conflicts to be
resolved; re-stacked onto #467 (d03c852, on test-qwennext 11cac8c) with every commit signed off
(DCO). The branch used to carry a merge of the C1 branch whose merge commit also edited three
files; it is now linear, and those edits are the last commit, cf68fd9. The patch relative to
#467 is identical to the one measured below (git patch-id), and the final tree is byte-identical
to the pre-rebase tip. b0f4c5c addresses the review of this branch, and 0cceb84 switches the
launchers' device guard to the form the ROCm build already compiles. Test results below were
measured before the re-stack; 32b765e..11cac8c on the base is formatting, lint/docs/CI configuration and the logp
indexed-write fix; the arithmetic measured here is unchanged. The diff shown by GitHub
includes #466's and #467's commits until they merge.

Repository file:line refer to this branch (cf68fd9; the line numbers are those of 0cceb84,
which cf68fd9 does not shift in the files cited). vLLM paths are relative to the installed
vllm 0.30.0 package root.

Summary

Bitwise status: advances the GDN gated RMSNorm row of #428 §7.2 on the CUDA track
(alongside C1's RMSNorm work in the PR below).
Claim levels, scoped to what this branch's tests and gates assert:

• L1 for Qwen3NextRMSNormGatedCudaOp: prefix slices in pytest (bf16, H=128, batch
  ∈ {1, 2, 8, 16, 32, 48, 64, 512} of 512 rows, one seed) and for dweight (fp32 inputs,
  batch ∈ {1, 8, 64, 512}); batch size, chunking, padding and permutation in the C3/C4
  gates (cuda_bf16, hidden 2048 / head-dim 128, one seed). The same gates cover the
  zero-centred CUDA op from the PR below.
• The gated forward's rstd is bitwise identical to the plain kernel's for the same
  x, asserted over 36 configurations.
• L0 is not separately tested for the gated CUDA op: no test repeats it.

Not bitwise vs vLLM. The CUDA op was not compared against vLLM. The vLLM-convention
PyTorch reference (from the PR below) differs from vLLM's two eager paths on 6/40 and
18/40 seeds (committed check) and from its compiled path on 17–18/40 in a one-off probe,
and vLLM's paths are not bitwise
equal to each other. The CUDA op and the PyTorch reference use different fixed-order
reductions and are compared only under the contract's reduction row.
L2 is not claimed.

y = x * rstd * (weight_offset + weight) * act(gate)

• Kernel. Every multiply is in fp32, with one cast at the store. This matches vLLM's
  RMSNormGated with norm_before_gate=True and group_size=None, which is what the
  GDN block constructs (model_executor/layers/mamba/gdn/qwen_gdn_linear_attn.py:487-494).
  The op has no parameter for either, so other values are not implemented rather than
  rejected.
• Activation. silu (swish is accepted as an alias) or sigmoid, fixed at
  construction and validated before the extension check (rmsnorm.py:191-196,
  :322-327). The registry constructs the default, silu (registry.py:1364). vLLM
  takes it from config.output_gate_type (default silu, qwen_gdn_linear_attn.py:480-485),
  so the registered op matches the released config, not every config. expf is used,
  not __expf (csrc/cuda/rmsnorm.cu:210-223); a build with
  KERNEL_ALIGN_USE_FAST_MATH=1 (off by default, setup.py:164-165) turns it back into
  the intrinsic.
• rstd. The forward copies the ungated kernel's sum-of-squares loop
  (rmsnorm.cu:120-131 and :248-259), with the same block_reduce_sum and the same
  choose_threads(H) launch shape. For a fixed H the reduction tree therefore does not
  depend on the row count, which is what L1 rests on. The 36-case identity test
  (tests/test_qwen3_next_norm.py:497-519) spans fp32/fp16/bf16 × H ∈ {128, 2048, 5120}
  × {silu, sigmoid} × offset ∈ {0, 1}; the H values cover both launch shapes (128
  threads at H=128; 512 threads with 4 or 10 serial columns).
• Backward. dx is a new kernel: the ungated dx with (w + offset) replaced by
  (w + offset) * act(z). dweight reuses rmsnorm_dweight_rows_fp32 and the
  ascending-row fp32 left fold, through the one _fold_dweight_rows helper both CUDA
  ops share (rmsnorm.py:8; tests/test_vjp_fp32.py:142-152 pins one
  reduce_rows_fp32( call per file). dgate is row-local, reduction-free and fp32.
• Parameter VJP uses the kernel's statistic. parameter_vjp_contributions_fp32
  takes rstd from _C.rmsnorm_gated_forward (rmsnorm.py:348-366), the statistic
  the backward uses; test_cuda_gated_parameter_vjp_contributions_match_the_fold
  asserts torch.equal with weight.grad. The plain op got the same change in the PR
  below; the Triton op still recomputes (see Notes).
• Registration. rms_norm_gated and qwen3_next_rms_norm are added to OP_SPECS
  (each with a cuda-sm90 candidate), operator_inputs.py, the registry (CUDA first,
  PyTorch reference on every other platform) and the WS1 registered-ops set. This is the
  first branch in the stack where check_operator --op accepts their names.
• Changes to existing code (details in Notes):
  • csrc/ops.cpp now TORCH_CHECKs the plain kernels' inputs. fp64 is now rejected
    by rmsnorm_forward and rmsnorm_backward_dx; on main they dispatched with
    AT_DISPATCH_FLOATING_TYPES_AND2, which includes double.
  • The USE_ROCM guard around the c10/cuda includes in rmsnorm.cu is removed, and
    the launchers use at::cuda::OptionalCUDAGuard as activation.cu does. The ROCm
    build has not been run (no ROCm device); see Notes for the static check.
  • The shared C3/C4 gate scripts gain --manifest, and adapters can be model-scoped.
• Corrections in this branch. cf68fd9 carries the edits of the former merge with the PR below
  and moves the gated tests onto its contract tolerances; b0f4c5c addresses the review (see the commit
  table).
• Question for the maintainers (also asked in the C1 PR): which source of truth
  should the CUDA strict profile use for forward arithmetic? See Notes.

Prior art & reuse decision

Measured with scripts/qwen3_next_norm_reuse_check.py, committed in this PR. rms_norm_gated.json was written from a clean tree at abb56c2 on an otherwise idle B200. The doc's "Existing implementations" section has the figure and the command. Batch invariance is bitwise and covers every row computed alone vs inside full batches of three sizes, the full 262144-row batch vs sub-batches covering every row, and a dense batch-size sweep. Accuracy is against FP64; latency is at the workload size. The C3/C4 column runs this repository's own gate scripts unchanged, with the CUDA candidate replaced by a subclass of this op whose forward and backward call the other library. The subclass keeps this op's FP32 dweight row contributions, so singleton-aggregate compares like with like.

Implementation	Batch-invariant	Forward correctly rounded	Worst grad err	Forward / forward + backward	C3/C4 gates
rl-kernel Qwen3NextRMSNormGatedCudaOp	yes	99.9989%	2.4e-03	235 µs / 115.3 ms	pass
rl-kernel PyTorch reference	yes	99.9990%	2.4e-03	772 µs / 1991 µs	—
transformers 5.17.0 Qwen3NextRMSNormGated	yes	65.4748%	5.6e-03	695 µs / 2093 µs	pass
FLA 0.5.2 layernorm_gated.rmsnorm_fn	yes	99.9987%	2.4e-03	177 µs / 882 µs	pass
FLA 0.5.2 fused_norm_gate.rms_norm_gated	no (247 sub-batches differ)	99.9987%	2.4e-03	93 µs / 865 µs	pass
vLLM 0.30.0 RMSNormGated.forward_cuda	no (3 rows differ; 3 sub-batches differ)	99.9988%	—	87 µs / —	—

Decision: open, and the reuse rule points to FLA's layernorm_gated.rmsnorm_fn. It is batch-invariant on every check, has vLLM's arithmetic (99.9987% correctly rounded, like this kernel) and a backward, passes the same gates, and takes 882 µs vs 115 ms forward + backward. The earlier reason for writing our own was: "transformers' arithmetic differs from vLLM's, and vLLM's has no backward". That no longer holds. Two earlier statements here were also wrong: vLLM's RMSNormGated.forward_cuda is not batch-invariant, and FLA's fused_norm_gate passes the gates but is not batch-invariant at the 262144-row workload. The gates use small shapes, which is why the checks above test every row and the full batch. This kernel's only remaining advantage is that it adds no dependency. Question for @inaniloquentee: switch to FLA's rmsnorm_fn, or keep this kernel?

Comparison charts

B200, head dim 128, BF16	rl-kernel CUDA	PyTorch reference	transformers (cast-first)	vLLM RMSNormGated*
rows differing alone vs in a batch, forward / dx,dgate (of 768)	0 / 0	0 / 0	0 / 0	0 / n/a
forward elements correctly rounded vs the golden	99.999%	99.999%	65.6%	99.999%
forward, 262144 rows	235 µs	774 µs	697 µs	81 µs
backward, 262144 rows	114 ms	1.4 ms	1.5 ms	n/a

* forward only. docs/usage/evidence/qwen3-next-rms-norm-gated-b200/report.json, written by scripts/qwen3_next_norm_evidence.py from a clean tree at 822b085 on an otherwise idle B200; the same report re-measures the zero-centred op.

Files

file	commit	status
csrc/cuda/rmsnorm.cu	b11b957, 7dd291a, aaf0986, 0cceb84	gated forward and dx kernels (:230, :279) and launchers (:457, :497); USE_ROCM include guard removed (7dd291a); offset added only when nonzero (aaf0986, :270, :306, :320); six launchers use at::cuda::OptionalCUDAGuard (0cceb84; :391, :428, :467, :507, :543, :573)
csrc/ops.cpp, rl_engine/_C.pyi	b11b957, 7dd291a, b0f4c5c	rmsnorm_gated_forward / _backward_dx bindings (:830-838); input checks (:313-334); duplicate dim/size checks dropped (b0f4c5c)
rl_engine/kernels/ops/cuda/norm/rmsnorm.py	b11b957, 7dd291a, b0f4c5c	RMSNormGatedCuda, Qwen3NextRMSNormGatedCudaOp (:300); activation as a constructor argument, dgate signed zero (b0f4c5c, :270-273, :322-327)
rl_engine/kernels/ops/pytorch/norm/qwen3_next_rms_norm.py	7dd291a, cf68fd9	gate dtype/device check; docstrings point at the gated page (cf68fd9)
rl_engine/kernels/registry.py	b11b957	OpBackend entries (:161-171); cuda lists (:609-616)
rl_engine/kernels/gtest/operator_specs.py, operator_inputs.py	b11b957	specs (:49-78); gated inputs follow --head-dim (operator_inputs.py:98-114)
rl_engine/kernels/gtest/gradient_adapters.py	8df1ffb	C3/C4 adapters, scoped to the Qwen3-Next model
rl_engine/testing/qwen3_next_norm_manifest.json, qwen3_next_workload.py	8df1ffb, b0f4c5c	norm-only workload manifest and its validator; SPDX header (b0f4c5c)
rl_engine/testing/ws1_workload.py	8df1ffb, b0f4c5c	load_manifest dispatches on scope (:267-272); workload_report() (b0f4c5c, :276-288)
scripts/check_{forward,gradient}_invariance.py	8df1ffb, b0f4c5c	--manifest (with help) and validate_norm_dimensions; report via workload_report() (b0f4c5c)
ci/run_ws1_gtest.sh	8df1ffb, b0f4c5c	Qwen3-Next stage, four explicit commands (:79-88)
tests/test_qwen3_next_norm.py	b11b957, 7dd291a, aaf0986, 5eaeca8, cf68fd9, b0f4c5c	76 cases added here (141 total; 65 from the PR below)
rl_engine/tests/test_dispatch.py	b11b957, 4ea1611, b0f4c5c	4 cases: priority and missing-extension fallback for both ops (:264-325)
tests/test_qwen3_next_workload.py	8df1ffb, b0f4c5c	7 cases (new)
tests/test_ws1_ascend_closeout.py, tests/test_ws1_gtest_gpu.py	8df1ffb, b11b957	skip model-scoped adapters, plus one new test; registered-ops set
docs/operators/qwen3-next-rms-norm-gated.md, docs/.nav.yml, docs/operators/README.md	b11b957, 7dd291a, b0f4c5c	operator page; contract pointer and corrected claims (b0f4c5c)
docs/operators/qwen3-next-rms-norm.md	b11b957, cf68fd9	registration and check_operator restored after the merge

commit	what
b11b957	gated CUDA kernel (forward + dx), autograd wrapper, gtest specs and registry entries for both ops, operator doc
7dd291a	input boundary checks in csrc/ops.cpp (also for the plain kernels), and the parameter-VJP rstd taken from the kernel
8df1ffb	Qwen3-Next workload manifest, C3/C4 adapters, and a Qwen3-Next stage in ci/run_ws1_gtest.sh
aaf0986	keeps -0.0 weights bit-exact in the gated kernels when weight_offset == 0
4ea1611	dispatch tests for qwen3_next_rms_norm
5eaeca8	the gated-vs-plain rstd identity test swept to 36 cases. Its message was written before its GPU run ("Not yet run on a GPU"); the results below supersede it
cf68fd9	the edits that used to live in the merge of the PR below (now a plain commit at the top of the branch). They resolve three statements the stacking made false: the decoder-norm page again states registration and the check_operator command, the gated tests use _forward_tol (bf16 reduction row, 5e-2/2e-2, looser than the private 2e-2/1.6e-2 they had), and the reference docstrings name the gated page
b0f4c5c	review fixes: gated page points to the contract and labels its one-off figures; duplicate TORCH_CHECKs dropped; workload_report() reads full_model_evidence from the manifest; module-level import and --manifest help; dispatch tests parametrized and resolved for device="cuda"; SPDX headers; explicit gate commands; activation as a constructor argument; dgate signed zero. Three new tests. Its message also predates its GPU run
0cceb84	the six launchers outside the USE_ROCM block switch from c10::cuda::CUDAGuard to at::cuda::OptionalCUDAGuard(device_of(...)), the form activation.cu uses in the ROCm build; same device source, same behavior on CUDA

Test

MAX_JOBS=32 TORCH_CUDA_ARCH_LIST=10.0 RL_KERNEL_REQUIRE_EXT=1 \
    pip install --no-build-isolation --no-deps -e .
python -m pytest tests/test_qwen3_next_norm.py -q -p no:randomly
python -m pytest rl_engine/tests/test_dispatch.py -q -p no:randomly
python -m pytest tests/test_qwen3_next_workload.py -q -p no:randomly
python -m pytest tests/check_qwen3_next_norm_providers.py -q -p no:randomly   # needs vLLM 0.30.0
python -m pytest tests/ rl_engine/tests/ -q -p no:randomly -rfE \
    --ignore=tests/test_rocm_aiter_api_contract.py
python scripts/check_operator.py --op rms_norm_gated --candidate cuda --device cuda --dtype bf16 \
    --batch 2 --seq 16 --head-dim 128 --seed 123 --check-grad
python scripts/check_operator.py --op qwen3_next_rms_norm --candidate cuda --device cuda --dtype bf16 \
    --batch 2 --seq 16 --normalized-dim 4096 --seed 123 --check-grad

# C3/C4 gates, as in ci/run_ws1_gtest.sh:79-88
export RL_KERNEL_REQUIRE_EXT=1
PY=python3
QWEN3_NEXT_NORM_MANIFEST=rl_engine/testing/qwen3_next_norm_manifest.json
"$PY" scripts/check_forward_invariance.py --manifest "$QWEN3_NEXT_NORM_MANIFEST" \
  --op qwen3_next_rms_norm --candidate cuda --backend-profile cuda_bf16 --hidden 2048 --head-dim 128
"$PY" scripts/check_gradient_invariance.py --manifest "$QWEN3_NEXT_NORM_MANIFEST" \
  --op qwen3_next_rms_norm --candidate cuda --backend-profile cuda_bf16 --hidden 2048 --head-dim 128
"$PY" scripts/check_forward_invariance.py --manifest "$QWEN3_NEXT_NORM_MANIFEST" \
  --op rms_norm_gated --candidate cuda --backend-profile cuda_bf16 --hidden 2048 --head-dim 128
"$PY" scripts/check_gradient_invariance.py --manifest "$QWEN3_NEXT_NORM_MANIFEST" \
  --op rms_norm_gated --candidate cuda --backend-profile cuda_bf16 --hidden 2048 --head-dim 128

• That is the local install. The cluster built the same extension in place with the same
  environment variables (python setup.py build_ext --inplace).
• tests/test_rocm_aiter_api_contract.py is ignored because it fails to import on
  main: it imports _AITER_FWD_REQUIRED_KEYWORDS, which rocm/attention/flash_attn.py
  does not define. Not ignoring it aborts collection.
• check_operator uses the script's default shapes (scripts/check_operator.py:107-120),
  not the Qwen3-Next dimensions. The gated op takes its width from --head-dim, not
  --normalized-dim (operator_inputs.py:98-114). The C3/C4 gates run at the
  Qwen3-Next dimensions, and the seed (20260812) comes from the manifest.

Test results

Cluster B200 (sm_100), driver 580.126.20, torch 2.13.0+cu130, triton 3.7.1, vllm 0.30.0,
transformers 5.17.0, Python 3.12.14; extension built from source for sm_100. The main
baseline ran on a B200 node of the same type.

check	main (32b765e)	this branch (0cceb84)
full suite	17 failed, 2942 passed, 923 skipped	15 failed, 3103 passed, 923 skipped: no new failures, the same 2 fixed
check_operator rms_norm_gated / qwen3_next_rms_norm	—	pass_rate=1.0000 / pass_rate=1.0000 (and rms_norm 1.0000)
C3/C4 gates (4 commands above)	—	all 4 passed=True; 72 invariance and singleton-aggregate comparisons, all bitwise (max_abs=0), across batch size, chunk, padding and permutation
device guard on a second GPU	—	with cuda:0 current, all six launchers (plain fwd/dx/dw, gated fwd/dx) on cuda:1 inputs write to cuda:1 and are bitwise equal to the same calls on cuda:0; the current device is unchanged afterwards
real pre-commit (pinned hooks, Python 3.10)	—	passes on the 15 files changed by cf68fd9 and b0f4c5c (hook environments built with Python 3.10.20) and on 0cceb84's one file; earlier commits in the 4ddbaa0 details

Failure sets are compared by test ID against the main baseline; the branch run used the
same B200 node as the baseline. The device-guard check is a one-off script (not in this
PR); it calls the extension's six launchers directly.

An earlier full run at b0f4c5c, on a different node, had one failure not on main:
tests/test_weight_sync_bridge.py::test_shared_memory_bridge_tensor_alias_is_visible_across_processes,
whose spawned child died in SemLock._rebuild with FileNotFoundError (the semaphore was
gone from /dev/shm). This PR touches no weight-sync code; the test passed 5/5 when rerun
alone on another node, and it passes in the 0cceb84 run above.

Targeted tests and gate output (b1e2efd)

tests/test_rms_norm.py                         57 passed, 72 skipped in 14.12s
tests/test_qwen3_next_norm.py                  141 passed in 9.03s
tests/test_qwen3_next_workload.py              7 passed in 4.13s
tests/test_ws1_gtest_gpu.py                    9 passed in 54.17s
tests/test_vjp_fp32.py                         50 passed in 5.58s
rl_engine/tests/test_dispatch.py               17 passed in 5.87s
tests/check_qwen3_next_norm_providers.py       9 passed, 14 warnings in 62.98s (0:01:02)
rms_norm               suite=rms_norm passed=True pass_rate=1.0000
rms_norm_gated         suite=rms_norm_gated passed=True pass_rate=1.0000
qwen3_next_rms_norm    suite=qwen3_next_rms_norm passed=True pass_rate=1.0000
op=qwen3_next_rms_norm profile=cuda_bf16 candidate=rl_engine.kernels.ops.cuda.norm.rmsnorm.Qwen3NextRMSNormCudaOp::cuda passed=True
op=qwen3_next_rms_norm profile=cuda_bf16 candidate=rl_engine.kernels.ops.cuda.norm.rmsnorm.Qwen3NextRMSNormCudaOp::cuda passed=True
op=rms_norm_gated profile=cuda_bf16 candidate=rl_engine.kernels.ops.cuda.norm.rmsnorm.Qwen3NextRMSNormGatedCudaOp::cuda passed=True
op=rms_norm_gated profile=cuda_bf16 candidate=rl_engine.kernels.ops.cuda.norm.rmsnorm.Qwen3NextRMSNormGatedCudaOp::cuda passed=True

Each gate prints one accuracy, invariance or singleton_aggregate line per comparison; the four logs total 72 invariance and singleton-aggregate comparisons, all max_abs=0.

Failure IDs: main (32b765e) vs this branch (b1e2efd), cluster

main (32b765e): 17 failed
  [fixed below] rl_engine/tests/test_dispatch.py::test_npu_registry_preserves_per_operator_cpu_fallbacks
  tests/distributed/test_rocm_attention_transport.py::test_rccl_adapter_world_sizes_match_the_shared_collective
  tests/test_attention_correctness.py::test_strict_rocm_aiter_ck_direct_decode_rejects_ignored_output
  tests/test_attention_correctness.py::test_strict_rocm_aiter_ck_direct_decode_uses_callers_output
  tests/test_attention_correctness.py::test_strict_rocm_aiter_ck_reuses_immutable_provenance_inputs
  tests/test_attention_dispatch.py::test_implementation_kind_policy_filters_without_marking_fallback
  tests/test_attention_dispatch.py::test_registered_backend_resolves_with_provenance
  tests/test_cross_config_cli.py::test_run_uses_only_cpu_and_resumes_when_cuda_is_available
  tests/test_cross_config_runner.py::test_cpu_smoke_cases_preserve_read_only_scoring_and_exact_provenance
  tests/test_cross_config_runner.py::test_runner_resumes_valid_attempt_and_retries_after_identity_or_tensor_change
  tests/test_distributed_grpo_loss.py::TestSingleRank::test_dispatch_resolves_this_backend
  tests/test_linear_logp.py::test_triton_det_tp_matches_single_rank_and_replicates[2]
  [fixed below] tests/test_rms_norm.py::test_registry_dispatches_rms_norm
  tests/test_rocm_logprob_backend.py::TestFusedKernelPath::test_tile_stats_read_input_dtype_exactly[triton]
  tests/test_swiglu.py::test_autograd_wrapper_contiguity_and_gradient_routing[True-needs_grad2]
  tests/test_ws1_candidate_evidence.py::test_ws1_cuda_and_triton_candidate_runtime_provenance
  tests/test_ws1_chain_integration.py::test_row_local_linear_vjp_matches_per_row_outer_and_gemv

this branch (b1e2efd): 15 failed, exactly the 15 main failures not marked [fixed below]

Mutation check, measured at 4ddbaa0

The rstd identity test is meant to fail if anything perturbs the gated statistic. A separate run
checked that at 5eaeca8: it added +1e-4f to each square in the gated kernel's
sum of squares and rebuilt. The rstd test then failed in all 36 configurations
(36 failed, 100 deselected), so the test detects a perturbed gated statistic.

The edited line, at 5eaeca8 (git show 4ddbaa0:csrc/cuda/rmsnorm.cu | sed -n 245,256p):

251:        local_sum += xv * xv;        // inside rmsnorm_gated_fwd_kernel

At b0f4c5c the same line is :254 (the PR below added a three-line comment at
:146-148; the plain kernel's copy at :125 is untouched). To repeat on this branch:

sed -i '254s/local_sum += xv \* xv;/local_sum += xv * xv + 1e-4f;/' csrc/cuda/rmsnorm.cu
git diff --stat   # one line changed in csrc/cuda/rmsnorm.cu
MAX_JOBS=32 TORCH_CUDA_ARCH_LIST=10.0 RL_KERNEL_REQUIRE_EXT=1 \
    pip install --no-build-isolation --no-deps -e .
python -m pytest tests/test_qwen3_next_norm.py -q -p no:randomly -k rstd_is_bitwise
git checkout csrc/cuda/rmsnorm.cu   # then rebuild

At 5eaeca8 the file collected 136 tests, hence 100 deselected; at b0f4c5c it collects
141. The recipe has not been re-run at b0f4c5c.

Mutation checks for the review fixes, measured at 257007c

Two Python-only mutations (no rebuild), each run on its own against the full
tests/test_qwen3_next_norm.py on a B200 with _C loaded from the tree under test:

mutation	edit	result
dgate adds the offset unconditionally	sed -i -e '271s/scale = weight.float()$/scale = weight.float() + ctx.weight_offset/' -e '272,273d' rl_engine/kernels/ops/cuda/norm/rmsnorm.py	3 failed, 138 passed: exactly test_cuda_gated_dgate_keeps_signed_zero_weight for fp32, fp16 and bf16
swish mapped to sigmoid	sed -i '188s/"swish": 0/"swish": 1/' rl_engine/kernels/ops/cuda/norm/rmsnorm.py	1 failed, 140 passed: exactly test_cuda_gated_swish_is_an_alias_for_silu

Each new test fails when the behavior it pins is removed, and no other test in the file
catches either change. Restore with git checkout rl_engine/kernels/ops/cuda/norm/rmsnorm.py.

Earlier results at 4ddbaa0 (and local results at de58159)

Cluster, 5eaeca8, same software as above. Each run built _C from its own clean
snapshot of the ref and refused to run unless rl_engine._C.__file__ was inside that
snapshot.

• Full suite: 15 failed, 3098 passed, 923 skipped; no new failures
  against main, and the two fixed by the bottom PR stay fixed. Arithmetic: 2942 + 2
  fixed + 154 newly collected (4036 − 3882) = 3098; 83 of the 154 are added in this PR.
• Targeted pytest at 5eaeca8: test_qwen3_next_norm.py 136 passed (71 new here,
  incl. the 36 rstd cases); test_dispatch.py 17 passed (4 new);
  test_qwen3_next_workload.py 7 passed; check_qwen3_next_norm_providers.py 9 passed;
  test_rms_norm.py 57 passed, 72 skipped; test_ws1_gtest_gpu.py 9 passed;
  test_vjp_fp32.py 50 passed.
• C3/C4 gates: all four report passed=True. All 72 comparisons are
  bitwise (max_abs=0): 68 invariance pairs across batch size, chunking, padding and
  permutation, plus 4 singleton-aggregate checks of dweight, which supply dweight's
  batch-size coverage. This was the first time these gates ran anywhere; CI has not
  reached them.
• Mutation check: above.
• check_operator, without shape flags (the defaults above): rms_norm_gated,
  qwen3_next_rms_norm and rms_norm, each passed=True pass_rate=1.0000. The
  job is not recorded.

Local, aaf0986: 2× B200, same software; extension built with
-gencode=arch=compute_100,code=sm_100. The _C it loaded was built from 82e6c16
(git diff --stat de58159 82e6c16 -- csrc/ is empty); that build has since been deleted,
so this cannot be re-checked. The two commits after aaf0986 and before the merge
change only tests.

full suite, local main (32b765e): 19 failed, 2940 passed, 923 skipped
full suite, local de58159:        17 failed, 3059 passed, 923 skipped   (no new failures)

main has two fewer failures on the cluster node than locally; each comparison is
against the same-environment baseline. Measured at aaf0986 against main: real
pre-commit, no new findings (also clean on the two later test commits);
mypy --ignore-missing-imports rl_engine/, no new errors (not re-run since);
mkdocs build --strict, 8 warnings, the same 8 as main.

Notes

Dispatch: construction failure falls through to the reference

Qwen3NextRMSNormGatedCudaOp.__init__ checks for the compiled symbols
(rmsnorm.py:325-327). The registry's _load_backend (registry.py:1372) only catches
import and attribute errors, but _get_or_create_backend (:1353-1370) skips a backend
whose construction raises. Raising in __init__ therefore lets the CUDA-first list fall
through to the PyTorch reference on a build without the extension. Neither runtime hook
(_adjust_priority_from_env, _adjust_priority_for_hardware) inserts another backend
for these two ops.

rl_engine/tests/test_dispatch.py:284-325 covers both ops. Since b0f4c5c the
fallback test resolves for device="cuda", so the CUDA-first list is walked even on a
CPU-only host, and it asserts the CUDA backend is in _failed_backends. It is skipped on
HIP builds.

Both specs carry a cuda-sm90 candidate, as rms_norm, qk_norm and lm_head do
(det_gemm, also a reduction spec, does not). Without it, --candidate cuda-sm90 fails
with a KeyError.

Changes to existing code, in detail

• csrc/ops.cpp (7dd291a; duplicates removed in b0f4c5c), checks shared by the
  plain and gated entry points (:313-334):
  • x must be fp32, fp16 or bf16 (fp64 now rejected by rmsnorm_forward and
    rmsnorm_backward_dx); weight must have the x dtype or be fp32.
  • Backward: dy must have the x dtype, and rstd must be fp32.
    rmsnorm_backward_dw has these checks plus device, mask and H checks, but no x
    dtype restriction.
  • All: tensors on the same device (including mask), and H > 0.
  • The launchers that lacked them gained a CUDAGuard and
    C10_CUDA_KERNEL_LAUNCH_CHECK; the left-fold launcher already had them. The per-row
    launchers and the chunked partial_dw launcher return early when T == 0.
  • b0f4c5c drops the dim/size checks rmsnorm_check_weight already performs; error
    messages for those cases now come from it, and no test matches the removed messages.
• USE_ROCM guard (7dd291a, 0cceb84). setup.py compiles rmsnorm.cu for ROCm
  as well. Static check only, no ROCm device: PyTorch's hipify (extension mode)
  translates the file without error; the two headers and C10_CUDA_KERNEL_LAUNCH_CHECK
  are already used unguarded by sources the ROCm build compiles (activation.cu,
  deterministic_attention.cu, the logp kernels); and since 0cceb84 the launchers use
  the same at::cuda::OptionalCUDAGuard as activation.cu. The only c10::cuda::CUDAGuard
  left is inside the USE_ROCM-excluded left-fold block. A ROCm build has not been run.
• Signed zero. The gated kernels add weight_offset only when it is nonzero
  (aaf0986), as the plain kernels do after the PR below. Since b0f4c5c the Python
  dgate path does the same (rmsnorm.py:270-273), pinned by
  test_cuda_gated_dgate_keeps_signed_zero_weight (3 dtypes).
• Shared gate scripts (8df1ffb, b0f4c5c). scripts/check_{forward,gradient}_invariance.py
  gain --manifest, and their JSON report gains a workload block for every op.
  validate_norm_dimensions returns immediately for any manifest other than the
  Qwen3-Next one (qwen3_next_workload.py:87-93). Since b0f4c5c,
  workload.full_model_evidence is read from the manifest: False for the Qwen3-Next
  manifest, None for the Dense manifest, which declares none (it was hard-coded
  False for every op).
• rl_engine/testing/ws1_workload.py: load_manifest dispatches validation on the
  manifest's scope, and _validate_model_identity takes the fingerprint as a
  parameter (:315-320).
• Shared adapter semantics: adapters can be model-scoped. An existing Ascend test
  (tests/test_ws1_ascend_closeout.py:195-199) skips adapters scoped to another model,
  and a new test (:207) asserts those resolve to absent_not_required.

Where the manifest's weight hashes come from

rl_engine/testing/qwen3_next_norm_manifest.json pins Qwen/Qwen3-Next-80B-A3B-Instruct
at revision 9c7f2fbe…, with 41 shard SHA-256s and sizes, the index file's SHA-256, and a
content_hash. How these values were first obtained is not recorded on this branch
(8df1ffb's message is subject-only), and nothing on the branch re-derives them from
files. What the validator checks (ws1_workload.py:337-369, called from
validate_norm_manifest, qwen3_next_workload.py:44) is internal consistency only:

• every shard digest and index_sha256 is 64 lowercase hex characters;
• weight_files_total_size_bytes equals the sum of the shard sizes;
• content_hash equals weight_snapshot_hash over the sorted (filename, sha256, size)
  records (:1135-1139).

The values are, however, reproducible from public Hugging Face Hub metadata at that
revision: all 41 shard SHA-256s and sizes equal the LFS oid/size of the revision's 41
.safetensors files; index_sha256 is the SHA-256 of its model.safetensors.index.json;
total_size_bytes is that index's metadata.total_size; and content_hash recomputes.
No weight bytes were downloaded, so this relies on Hugging Face's LFS digests.

REV=9c7f2fbe84465e40164a94cc16cd30b6999b0cc7
curl -sSL "https://huggingface.co/api/models/Qwen/Qwen3-Next-80B-A3B-Instruct/tree/$REV" -o tree.json
curl -sSL "https://huggingface.co/Qwen/Qwen3-Next-80B-A3B-Instruct/resolve/$REV/model.safetensors.index.json" | sha256sum
python - <<'PY'
import json
from rl_engine.testing.ws1_workload import weight_snapshot_hash
hf = {e["path"]: e.get("lfs") or {} for e in json.load(open("tree.json"))}
ws = json.load(open("rl_engine/testing/qwen3_next_norm_manifest.json"))["model_identity"]["weight_snapshot"]
print(sum(hf[s["filename"]].get("oid") == s["sha256"] and hf[s["filename"]].get("size") == s["size_bytes"]
          for s in ws["shards"]), "/", len(ws["shards"]))
print(weight_snapshot_hash(ws["shards"]) == ws["content_hash"])
PY

The gates never load weights: they use synthetic inputs at the checkpoint's dimensions
(provenance_boundary.runtime_verified: false, full_model_evidence: false). The Dense
path's verify_hf_weight_snapshot (rl_engine/alignment/qwen3_dense.py:548) has no
Qwen3-Next counterpart.

On exactness against vLLM, and the question for the maintainers

vLLM has three numerical paths for this norm, and none is bitwise equal to another:
A. eager forward_native (PyTorch ops); B. FLA forward_cuda (Triton); C.
forward_native compiled by Inductor inside the model graph.

• Default (inductor) mode → C. custom_ops defaults to "none"
  (config/vllm.py:1608-1615). The norm is called at qwen_gdn_linear_attn.py:856,
  outside the splitting op vllm::qwen_gdn_attention_core, so it is traced into the
  model graph.
• enforce_eager → B. custom_ops becomes "all" (config/vllm.py:1615).

A vs B (committed in tests/check_qwen3_next_norm_providers.py, from the PR below and
not changed here): over 40 seeds (bf16, head_v_dim=128, 512 rows, one shape, B200)
they disagreed on 21, worst 1.56e-2. In fp32 they differ on about 36% of elements,
under an asserted bound of 1e-5. The file bounds the eager gaps rather than asserting
equality.

Conventions. vLLM's fp32 weight multiply is Qwen3NextRMSNormGatedOp;
transformers' cast-first multiply is Qwen3NextRMSNormGatedHFOp. One earlier
measurement, with no committed script, found them differing on 35% of elements in bf16,
max 6.25e-2 (docs/operators/qwen3-next-rms-norm-gated.md:91-94, one seed). The
committed test asserts only that they differ (> 1e-3) in bf16 and agree bitwise in
fp32.

Question (RFC #428 §0 item 1): which source of truth should the CUDA strict profile
use for forward arithmetic?

• The RFC's §0 profile table and §7.2 ("GDN gated RMSNorm | Shared forward") point to a
  shared vLLM forward. For this norm that means the FLA kernel or the compiled path,
  depending on mode.
• The existing Qwen3 dense strict profile instead patches vLLM's RMSNorm to PyTorch
  eager arithmetic on CUDA (rl_engine/integrations/vllm_runtime.py:1283-1304,
  :1415); on ROCm strict_rms_norm goes to rocm.rmsnorm instead
  (rl_engine/kernels/ops/pytorch/norm/rms_norm.py:17-21, and :44-48 with a residual).

The answer also decides which gated convention is the strict default.

The Triton op still has the split the plain CUDA op had on main: its parameter-VJP
hook recomputes rstd with mean(-1) (rl_engine/kernels/ops/triton/rmsnorm_triton.py:164-169)
while its backward uses the saved rstd (:127-130). That is how it is on main, and
it is left for a separate change.

Diagnostic, not reproducible from this branch: compiled path and VLLM_BATCH_INVARIANT=1

From a one-off standalone probe (not committed, not an engine run):

• C vs A: 20/40 seeds differ;
• the gated PyTorch reference vs C: 17–18/40;
• the gated PyTorch reference vs A: 6/40.

On VLLM_BATCH_INVARIANT=1:

• It does not reach this norm in either mode. Under enforce_eager the FLA kernel never
  calls aten.mean.
• In the standalone compile, output was bitwise identical with the flag on and off
  (40/40), with 0 calls to the batch-invariant mean.
• Calling forward_native directly in eager mode with the flag on also left the output
  bitwise unchanged (0/40).

The same probe found no prefix-slice batch-invariance failure for vLLM's eager path or
its dim-0-dynamic compile (seeds 0–7, n up to 256). See the C1 PR for the full table and
its scope limits.

What CI will and will not run

As of 2026-10-01 no CI path executes these tests, before or after merge.

• On main (32b765e and the current 1968a87), CI-Pipeline's linting fails at
  Run pre-commit hooks, so unit-tests is skipped. Docs fails at both commits too.
• WS1-chain-GPU and ws1-gtest-gpu stop at Configure runpodctl. The cause is step
  order, not a recent release: runpodctl config --apiKey, run as the first runpodctl
  call on a fresh runner, finds no config file (run 36835086246 logs
  'runpodctl config' is deprecated then error saving config, reproduced locally with
  v2.14.0 on an empty HOME). ws1-gtest-gpu has never succeeded: as of 2026-10-01,
  122 runs (69 failed, 40 skipped, 13 action_required), and its first run (2026-08-19)
  already failed at this step. A separate fix is being prepared.
• gpu-ci (pull_request_target only, gpu-ci.yml:4; label needs-gpu-ci) uses the
  same command (:50) but runs runpodctl version first, which creates the config
  file, so it got past setup on its last run that reached
  RunPod (2026-09-11, run 34585491929) and then failed at pod create. No run since, so
  whether it still gets past setup is unverified. Its pytest tests/
  (ci/run_gpu_ci.sh:133) would also stop at the aiter collection error.
• ws1-chain-npu was queued on 1968a87 and cancelled on 32b765e.

If those are fixed, the workflows' scripts would run:

1. ci.yml (needs: linting): tests/test_qwen3_next_norm.py and
   rl_engine/tests/test_dispatch.py on a CPU-only runner, so the CUDA cases skip; the
   dispatch fallback test does walk the CUDA list there. Not test_qwen3_next_workload.py.
2. ws1-gtest-gpu.yml: same-repo PRs and push to main, skipped for fork PRs
   (:59); this branch touches its paths. It would run the four Qwen3-Next gates
   (ci/run_ws1_gtest.sh:79-88) and tests/test_ws1_gtest_gpu.py, none of the other
   pytest files above. It runs on sm_86 (RTX A4000) and sm_90 (H100), not sm_100, under
   set -euo pipefail with the Qwen3-Next stage last, so any earlier failure skips it.
3. ws1-chain-gpu.yml: push and PR to main/test, no paths filter, skipped for
   fork PRs (:46); maintainers can dispatch it on a fork's commit (:14-24). Its chain
   constructs RMSNormCudaOp directly (rl_engine/alignment/qwen3_dense.py:374-396), so
   it would execute the plain-kernel input checks this PR adds in csrc/ops.cpp.
4. gpu-ci.yml: with the collection error fixed, it would collect the CUDA cases but
   not the check_ file.

Hardware, base and stacking

• sm_100 (Blackwell), not sm_90. Per RFC §2.2 no claim is made across H100/B200.
• Stacked on feat/cuda-qwen3-next-c1-norm, which is on
  fix/registry-cuda-rmsnorm-dispatch; both must merge first, and this branch contains
  their commits. cf68fd9 merges cleanly into the current upstream/test-qwennext (11cac8c,
  git merge-tree --write-tree). One further PR builds on this one.

Known review items left as they are

• Duplicated sum-of-squares loop. The gated forward copies the plain kernel's
  sum-of-squares loop, block_reduce_sum and rsqrtf (rmsnorm.cu:248-259 vs
  :120-131), and the gated dx copies the dot loop (:302-309 vs :176-182). The
  bitwise rstd guarantee therefore rests on the 36-case test rather than on shared
  code. A shared device function is a follow-up.
• Private validator imports. qwen3_next_workload.py:9-18 imports six
  underscore-private validators from ws1_workload, and ws1_workload.py:268 imports
  back inside load_manifest to avoid the import cycle.
• Hard-coded dimensions. validate_norm_dimensions checks hidden != 2048 or head_dim != 128 (qwen3_next_workload.py:90), values already present in NORM_OPS
  (:37) and FINGERPRINT["linear_value_head_dim"] (:31).
• 5eaeca8's and b0f4c5c's messages say their CUDA tests had not yet run on a GPU;
  the results above supersede them. History on this branch is not rewritten.

None of these changes behavior. They are left for follow-ups, because any commit here
would have to be merged forward into the c6 branch stacked on it.

Summary by CodeRabbit

• New Features

  • Added Qwen3-Next zero-centred and gated RMSNorm operations, with CUDA and PyTorch support, configurable weight offsets, and SiLU or sigmoid gating.
  • Added fallback to the PyTorch implementation when CUDA support is unavailable.
  • Added operator documentation and workload-specific validation.
  • Added benchmark and comparison reports for accuracy, invariance, and performance.

• Bug Fixes

  • Strengthened input validation and handling of empty batches for RMSNorm operations.

• Tests

  • Expanded coverage for forward and gradient behavior, backend dispatch, invariance, and compatibility with reference implementations.

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📝 Walkthrough

📝 Walkthrough

Walkthrough

The change adds zero-centred and gated RMSNorm operators for Qwen3-Next, with CUDA and PyTorch implementations and backend dispatch. It also adds a pinned norm-only workload manifest, validation, invariance checks, tests, benchmark tooling, evidence reports, and operator documentation.

Changes

Qwen3-Next RMSNorm

Layer / File(s)	Summary
CUDA API and kernels csrc/cuda/rmsnorm.cu, csrc/ops.cpp, rl_engine/_C.pyi, rl_engine/kernels/ops/cuda/norm/rmsnorm.py, tests/test_rms_norm.py	RMSNorm forward and input-gradient APIs accept a weight offset. Gated forward and input-gradient APIs support SiLU and sigmoid. CUDA kernels add offset-aware scaling, empty-row returns, and launch checks. The bindings declare API version 2.
Operator implementations and dispatch rl_engine/kernels/ops/pytorch/norm/*, rl_engine/kernels/registry.py, rl_engine/kernels/gtest/operator_inputs.py, rl_engine/kernels/gtest/operator_specs.py, rl_engine/tests/test_dispatch.py, tests/test_qwen3_next_norm.py, docs/operators/*, docs/.nav.yml, docs/operators/README.md	Adds PyTorch and CUDA operators for zero-centred and gated RMSNorm, plus CUDA-first dispatch with PyTorch candidates on other backends. Tests cover formulas, gradients, invariance, validation, and signed-zero behavior. Operator pages describe conventions, constraints, dispatch, and documented evidence.
Workload manifest and validation rl_engine/testing/qwen3_next_norm_manifest.json, rl_engine/testing/qwen3_next_workload.py, rl_engine/testing/ws1_workload.py, tests/test_qwen3_next_workload.py	Adds a pinned Qwen3-Next norm-only manifest and validation for model identity, fixtures, required operators, and dimensions. Manifest loading selects the scope-specific validator and can report workload metadata.
Invariance checks and gradient adapters rl_engine/kernels/gtest/gradient_adapters.py, scripts/check_forward_invariance.py, scripts/check_gradient_invariance.py, ci/run_ws1_gtest.sh, tests/test_ws1_ascend_closeout.py, tests/test_ws1_gtest_gpu.py, .github/workflows/ci.yml, .github/workflows/ws1-gtest-gpu.yml	Adds model-scoped gradient adapters and operator inputs. The invariance scripts accept workload manifests and include workload details in JSON output. CI adds the norm tests and manifest-based forward and gradient checks.
Provider checks and benchmark evidence tests/check_qwen3_next_norm_providers.py, scripts/qwen3_next_norm_evidence.py, scripts/qwen3_next_norm_reuse_check.py, scripts/plot_qwen3_next_norm_evidence.py, docs/usage/evidence/*	Adds provider comparison checks and CUDA tools that record accuracy, row invariance, gradient, and latency results. Adds benchmark reports and a plotting script.

Priority: ⬇️ Low

Estimated code review effort: 4 (Complex) | ~60 minutes

Change: Feature

Sequence Diagram(s)

sequenceDiagram
  participant OperatorRegistry
  participant Qwen3NextRMSNormCudaOp
  participant PyTorchReference
  OperatorRegistry->>Qwen3NextRMSNormCudaOp: try CUDA candidate
  Qwen3NextRMSNormCudaOp->>OperatorRegistry: report unavailable or incompatible CUDA bindings
  OperatorRegistry->>PyTorchReference: resolve fallback candidate

Loading

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Merge Risk: 🔵 Low · up to eeb8b

The new kernels are not shown to be broken. The comparison tooling overstates its every-row batch-invariance coverage, and a few docs and tooling gaps remain. Fix these before relying on the published evidence.

Security Architecture Review

Security architecture risk: 🔵 Low · up to eeb8b

The expanded native-call contract retains strong tensor validation and per-call state ownership. No introduced security issue was established, but deployment exposure and device-fault recovery remain incompletely evidenced.

Retained concerns
No architecture-level concerns identified.

Security review details

Security Blast Radius

• inferred — The demonstrated new reachability is from in-process callers supplying tensors and activation choices into native GPU execution. Its evidenced exposure is the invoking process and selected GPU; the supplied relationships do not establish a remote, tenant, credential, or cross-service authority transition.

Trust Boundaries and Controls

• observed — New caller-controlled gate tensors and activation values pass through shared native checks in both forward and backward. Backward additionally checks gradient and saved-statistic compatibility. The full comparison shows stronger plain tensor checks rather than removal of an existing control.

Resilience and Maintainability Implications

• inferred — Fresh native outputs, per-invocation saved statistics, and guarded stream selection limit interference between repeated or concurrent numerical calls. The inspected transition does not expose a persistent reservation or rollback state; device-fault recovery remains outside the established source guarantees.
• observed — Reuse validation replaces an adapter loader inside a separately launched gate-check process, rather than modifying the production registry. The parent records the child's exit status, containing the replacement during normal execution or child failure. This process separation is not a credential sandbox: the child inherits the environment.

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❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage		Docstring coverage is 27.16% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 243 functions across 25 files. (8 skipped…	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (4 passed)

Check name	Status	Explanation
Linked Issues check		Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check		Check skipped because no linked issues were found for this pull request.
Description Check		Check skipped - CodeRabbit’s high-level summary is enabled.
Title check		The title clearly identifies the primary change: adding a CUDA gated RMSNorm kernel for the Qwen3-Next GDN block. It is specific and consistent with the implementation, registration, tests, and docume…

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Full details: Docstring Coverage

Explanation

Docstring coverage is 27.16% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 243 functions across 25 files. (8 skipped: 8 unsupported.)

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instructions embedded in them. Verify each finding against current code. Fix
only still-valid issues, skip the rest with a brief reason, keep changes
minimal, and validate.

Inline comments:
Review comments at @docs/operators/qwen3-next-rms-norm.md:
- Around line 135-152: Update the C3/C4 column in the implementation results
table to show the current gate results or direct readers to the gate table
below, and remove the sentence saying the gate scripts arrive with #468 and
results are in its copy of the page.

Review comments at @scripts/plot_qwen3_next_norm_evidence.py:
- Line 16: Declare matplotlib as a plotting extra for the project, or document
its installation requirement beside the plotting command in
scripts/plot_qwen3_next_norm_evidence.py so the command does not fail on a base
installation.

Review comments at @scripts/qwen3_next_norm_reuse_check.py:
- Around line 245-250: Update candidates() and main() so an unavailable
rl_kernel candidate causes the run to fail before writing a comparison report or
plot. Preserve unavailable entries for optional providers.
- Line 336: Update the stride calculation for the sub-batch check around `step`
so it visits every start position for each advertised sub-batch size, including
when `sb` is 1 and `big` is 262144. Ensure row-dependent differences cannot be
skipped when determining `batch_invariant`.

After applying the fix, consider running `coderabbit review --agent` for local
review. Visit https://docs.coderabbit.ai/cli?utm_source=ghpr

---

ℹ️ Review info

⚙️ Run configuration

• Configuration used: defaults
• Review profile: CHILL
• Plan: Advanced
• Run ID: 3ff4d98c-8e0d-4baa-8d96-e6bcb1daff22

📥 Commits

Reviewing files that changed from the base of the PR and between b65426a and eeb8b0a.

⛔ Files ignored due to path filters (5)

• docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.png is excluded by !**/*.png
• docs/usage/evidence/qwen3-next-norm-reuse-b200/rms_norm_gated.png is excluded by !**/*.png
• docs/usage/evidence/qwen3-next-rms-norm-b200/figure.png is excluded by !**/*.png
• docs/usage/evidence/qwen3-next-rms-norm-gated-b200/figure-gated_rmsnorm.png is excluded by !**/*.png
• docs/usage/evidence/qwen3-next-rms-norm-gated-b200/figure-zero_centred_rmsnorm.png is excluded by !**/*.png

📒 Files selected for processing (19)

• .github/workflows/ws1-gtest-gpu.yml
• ci/run_ws1_gtest.sh
• csrc/cuda/rmsnorm.cu
• csrc/ops.cpp
• docs/operators/qwen3-next-rms-norm-gated.md
• docs/operators/qwen3-next-rms-norm.md
• docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm.json
• docs/usage/evidence/qwen3-next-norm-reuse-b200/qwen3_next_rms_norm_gates.json
• docs/usage/evidence/qwen3-next-norm-reuse-b200/rms_norm_gated.json
• docs/usage/evidence/qwen3-next-rms-norm-b200/report.json
• docs/usage/evidence/qwen3-next-rms-norm-gated-b200/report.json
• rl_engine/_C.pyi
• rl_engine/kernels/ops/cuda/norm/rmsnorm.py
• rl_engine/kernels/registry.py
• scripts/plot_qwen3_next_norm_evidence.py
• scripts/qwen3_next_norm_evidence.py
• scripts/qwen3_next_norm_reuse_check.py
• tests/test_qwen3_next_norm.py
• tests/test_rms_norm.py

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