Nidal bus system

docs/ip-briefs/axi_crossbar.md

@@ -35,14 +35,14 @@ Central AXI4 interconnect between managers and subordinates. Performs address de
 
 ### Performance Targets
 
-- **Clock:** **TBD** MHz (ASIC), **TBD** MHz (FPGA)
+- **Clock:** 100 MHz (FPGA)
 - **Throughput:** **1 beat/cycle** once granted (R & W)
 - **Latency (xbar-only):** addr → grant ≤ 2 cycles; read addr → first data ≤ 3 cycles beyond subordinate; last-W → B ≤ 3 cycles
 - **Arbitration:** **Round-robin;** starvation ≤ **N_M grants**
-- **Bursts:** **INCR**, max len **TBD**
-- **Outstanding:** per-manager **TBD R/TBD W**; backpressure only
-- **CDC:** each crossing adds **+TBD cycles;** throughput unchanged
-- **Reset:** READY may assert within ≤ **TBD cycles** after `rst_ni` deassert 
+- **Bursts:** **INCR**, max len 16
+- **Outstanding:** per-manager 2 R/2 W; backpressure only
+- **CDC:** each crossing adds 3-5 cycles; throughput unchanged
+- **Reset:** READY may assert within ≤ 2 cycles after `rst_ni` deassert 
 ---
 
 ### Behavior & Timing

docs/ip-briefs/plic_module_brief_v0.2.md

@@ -1,69 +1,74 @@
-# PLIC - Module Brief (v0.3)
+# PLIC - Module Brief (v1.0)
 
 **Owner:** Gavin Wiese  
 **RTL:** rtl/irq/plic.sv
 
 ### Purpose & Role
-The Platform-Level Interrupt Controller (PLIC) is placed near the CPU core. The PLIC manages and prioritizes external interrupt requests from up to 32 sources, forwarding only the highest-priority pending interrupt to the CPU. This allows the processor to efficiently handle asynchronous external events.
+The Platform-Level Interrupt Controller (PLIC) is placed near the CPU core. The PLIC manages and prioritizes external interrupt requests from up to `NSOURCES` sources, forwarding only the highest-priority pending interrupt to the CPU. This allows the processor to efficiently handle asynchronous external events.
 
 ### Parameters  
 
-- Number of interrupt sources: 32 (`NSOURCES`)  
-- Priority field width per source: 3 bits (`PRIO_WIDTH`)  
-- Interrupt ID width for claim/complete operations: `$clog2(NSOURCES)`  
+- Number of interrupt sources: `NSOURCES` (default 8)  
+- Priority field width per source: `PRIO_WIDTH` (default 3 bits)  
+- Interrupt ID width: `SRC_ID_WIDTH` (default 3 bits)  
 
 ### Interfaces (Ports)  
 
 | **Signal**           | **Dir** | **Width** | **Description**                                    |
 |----------------------|---------|-----------|----------------------------------------------------|
 | clk_i                | in      | 1         | System clock                                       |
 | rst_ni               | in      | 1         | Active-low asynchronous reset                     |
-| src_i                | in      | 32        | External interrupt sources                         |
-| priority_wdata       | in      | 96        | Data to write to all priority registers (32 × 3)  |
+| claim_req_i          | in      | 1         | CPU claim request pulse                           |
+| complete_i           | in      | 1         | CPU interrupt completion pulse                    |
+| src_i                | in      | NSOURCES  | External interrupt sources                         |
+| priority_wdata       | in      | NSOURCES × PRIO_WIDTH | Data to write to all priority registers  |
 | priority_we          | in      | 1         | Write enable for priority registers               |
-| enable_wdata         | in      | 32        | Data to write to enable register                   |
+| enable_wdata         | in      | NSOURCES  | Data to write to enable register                   |
 | enable_we            | in      | 1         | Write enable for enable register                  |
-| claim_wdata          | in      | 5         | Claim complete input                               |
-| claim_we             | in      | 1         | Write enable for claim completion                 |
 | ext_irq_o            | out     | 1         | Interrupt output to the CPU core                  |
-| claim_o              | out     | 5         | Current claimed interrupt ID                      |
+| claim_o              | out     | SRC_ID_WIDTH | Current claimed interrupt ID (1-based, 0 = none) |
 
 ### Reset/Init  
 
-An active-low asynchronous reset (`rst_ni`) is used for the PLIC. When reset is asserted (`rst_ni = 0`), all internal registers—including `priorities`, `enable`, `pending`, and `claim`—are cleared to 0, and the output signal `ext_irq_o` is deasserted.
+An active-low asynchronous reset (`rst_ni`) is used for the PLIC. When reset is asserted (`rst_ni = 0`), all internal registers—including `priorities`, `enable`, `pending`, and claim state—are cleared to 0, and the output signal `ext_irq_o` is deasserted.
 
 ### Behavior and Timing  
 
-The PLIC continuously monitors the 32 `src_i` interrupt lines. When one or more enabled interrupts are pending, the highest-priority source is selected, and `ext_irq_o` is asserted to signal the CPU core. Once the CPU completes the interrupt (signaled via `claim_we`), the pending bit for that interrupt is cleared and `ext_irq_o` deasserts. All operations are synchronous with the system clock, and `ext_irq_o` asserts one clock cycle after the conditions are met.  
+The PLIC continuously monitors the `src_i` interrupt lines. When one or more enabled interrupts are pending with nonzero priority and no interrupt is currently in service, the highest-priority source is selected and `ext_irq_o` is asserted to signal the CPU core.  
+
+When the CPU asserts `claim_req_i`, the PLIC outputs the highest-priority enabled pending interrupt ID on `claim_o` (1-based) and clears that interrupt’s pending bit. While an interrupt is in service, `ext_irq_o` remains deasserted.  
+
+When the CPU signals completion via `complete_i`, the in-service state is cleared, allowing the next pending interrupt (if any) to be delivered.  
+
+All operations are synchronous with the system clock.
 
 ### Programming Model
 
-The PLIC provides three sets of registers controlled via simple write-enable/data inputs:
+The PLIC provides two sets of registers controlled via simple write-enable/data inputs:
 
 - **`priority`** – Stores the priority of each interrupt source. Higher values indicate higher priority. Updated via `priority_wdata` and `priority_we`.  
 - **`enable`** – Determines which interrupt sources are enabled. Updated via `enable_wdata` and `enable_we`.  
-- **`claim`** – Contains the currently claimed interrupt ID. Writing to this register with `claim_wdata` and `claim_we` signals completion, clearing the pending bit.  
 
-All registers are accessible through the `_we` / `_wdata` inputs in this bus-free implementation.
+Claim and completion are handled via `claim_req_i` and `complete_i` handshake signals.
 
 ### Errors/IRQs
 
 | **IRQ**    | **Source** | **Trigger**                       | **Clear**                           |
 |------------|-----------|----------------------------------|-------------------------------------|
-| ext_irq_o  | src_i     | One or more enabled interrupts pending | Cleared when CPU signals completion via claim input |
+| ext_irq_o  | src_i     | One or more enabled interrupts pending with priority > 0 and no active claim | Cleared while in service; may reassert after completion |
 
 The PLIC does not generate additional internal error signals; all interrupts come from external sources.
 
 ### Performance Targets
 
-- `ext_irq_o` asserts within one clock cycle of a pending, enabled interrupt being detected.  
-- All internal registers (priority, enable, claim/complete, pending) update synchronously with the system clock.  
-- The PLIC can handle all 32 external sources without loss of pending interrupts.
+- `ext_irq_o` asserts when an enabled pending interrupt with nonzero priority exists and no interrupt is currently in service.  
+- All internal registers (priority, enable, pending, claim state) update synchronously with the system clock.  
+- The PLIC can handle all `NSOURCES` external sources without loss of pending interrupts.
 
 ### Dependencies
 
-The PLIC depends on `clk_i` to update internal registers and monitor interrupt sources, and on `rst_ni` to initialize registers. External interrupt lines (`src_i`) provide input events, and the PLIC drives the single interrupt output (`ext_irq_o`) to the CPU core. Register updates are controlled via `_we` / `_wdata` inputs.
+The PLIC depends on `clk_i` to update internal registers and monitor interrupt sources, and on `rst_ni` to initialize registers. External interrupt lines (`src_i`) provide input events, and the PLIC drives the single interrupt output (`ext_irq_o`) to the CPU core. Register updates are controlled via `_we` / `_wdata` inputs, and interrupt servicing uses the `claim_req_i` / `complete_i` handshake.
 
 ### Verification Links
 
-Verification for the PLIC is planned through simulation testbenches to confirm correct behavior of priority handling, enable bits, and the claim/complete mechanism. Testbenches will ensure that `ext_irq_o` asserts for the highest-priority pending interrupt, that pending bits are cleared after a claim/complete operation, and that the module responds correctly to reset (`rst_ni`).  
+Verification for the PLIC is planned through simulation testbenches to confirm correct behavior of priority handling, enable bits, and the claim/complete mechanism. Testbenches will ensure that `ext_irq_o` asserts for the highest-priority pending interrupt, that pending bits are cleared after a claim operation, and that the module responds correctly to reset (`rst_ni`).

gamingCPU.editorconfig

@@ -0,0 +1,17 @@
+root = true
+[*]
+charset = utf-8
+end_of_line = lf
+insert_final_newline = true
+trim_trailing_whitespace = true
+[*.{sv,svh,v,vh}]
+indent_style = space
+indent_size = 2
+max_line_length = 100
+[*.{c,h}]
+indent_style = space
+indent_size = 2
+max_line_length = 100
+[*.{yaml,yml,dts,dtsi,md}]
+indent_style = space
+indent_size = 2

rtl/bus/axi/axi_dcache_port.sv

@@ -1,6 +1,6 @@
 module axi_dcache_port #(
   // TODO: Parameter setups
-  parameter
+  parameter unsigned 
 )(
   // TODO: Port set up
   ports
@@ -9,6 +9,7 @@ module axi_dcache_port #(
   input logic clk_i,
   input logic rst_ni
 
+
 );
 
 endmodule

rtl/bus/axi/axi_icache_port.sv

@@ -1,14 +1,87 @@
+// import interconnect_pkg;
+
 module axi_icache_port #(
-  // TODO: Parameter setups
-  parameter
+
+  // System AXI Parameters
+  parameter int unsigned AXI_ADDR_WIDTH = 32,
+  parameter int unsigned AXI_DATA_WIDTH = 64,
+  parameter int unsigned AXI_ID_WIDTH   = 4,
+  parameter int unsigned AXI_USER_WIDTH = 1,
+
+
 )(
-  // TODO: Port set up
-  ports
 
-  // TODO: Input logic
+  // global clock and reset signals
   input logic clk_i,
   input logic rst_ni
+
+
+  // icache valid request and address
+  input logic                             ic_req_valid_i,
+  input logic[AXI_ADDR_WIDTH-1:0]         ic_addr_valid_i,
+
+  // I$ miss logic
+  input logic                             icache_miss_ar,
+  input logic                             icache_miss,
+
+
+  // axi address read signals
+  output logic [AXI_ADDR_WIDTH-1:0]       axi_mem_ar_o,
+  output logic axi_ar_valid_o, 
+  input logic axi_ar_ready_i, 
+  output logic [AXI_ADDR_WIDTH-1:0]       ar_addr, 
 
+
+  // axi read data signals
+  // TODO: figure out more needed parameters
+  input logic axi_mem_r_i,
+  input logic axi_r_ready_i, 
+  input logic axi_r_valid_i,
+  input logic [AXI_ADDR_WIDTH*4-1:0]      axi_mem_r_i,
+  input logic                             
+
+  typedef enum [2:0] {
+    IDLE,					  // Do nothing, wait for icache to miss
+    AR_SEND,				// cache requested a line, put it on araddr and set ARVALID to high
+    R_COLLECT,      // collect the requested data from the crossbar and send it to cache, once rlast is recieved, flip back to idle
+
+  } icache_port_state_e;
+
+  icache_port_state_e current_state, next_state;
+
+  // state transition
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      current_state <= IDLE;
+    end
+    else begin
+      current_state <= next_state;
+    end
+  end
+
+
+  // state transition logic
+  // TODO: finish the state transition logic
+  always_comb begin 
+    next_state = current_state;
+    case (current_state)
+      IDLE: begin
+        if (icache_miss && ) next_state = AR_SEND;
+
+      end
+
+      AR_SEND: begin
+        if () next_state = R_COLLECT;
+
+      end
+
+      R_COLLECT: begin
+        if () next_state = IDLE;
+
+      end
+    endcase
+
+  end
 );
 
 endmodule

rtl/bus/bridges/ahb_to_axi.sv

@@ -0,0 +1 @@
+//Divyesh Narra

rtl/bus/interconnect_pkg.sv

@@ -0,0 +1,21 @@
+//
+
+
+package interconnect_pkg;
+
+// AXI Data Widths
+parameter int unsigned AXI_ADDR_WIDTH = 32;
+parameter int unsigned AXI_DATA_WIDTH = 64;
+parameter int unsigned AXI_ID_WIDTH = 4;
+parameter int unsigned AXI_USER_WIDTH = 1;
+
+parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH/8;
+
+// Master IDs (TBD)
+
+// Address Map (TBD)
+
+// Cache Line
+
+
+endpackage