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cleaned up division module, added better comments to describe intent, still needs signed division and zero edge case
Added MUL and Division instructions
Cache branch
Interrupts RTL update
moved enums outside the module and defined them as Typedef
moved the import rv32_pkg line above module
updated clk and reg signals to clk_i and rst_ni
…-CPU-Project into nidal_bus_system
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Description
Progress on the instruction cache file so far. Not yet ready for review.