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adding riscv cycle counter #348

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adding riscv cycle counter #348

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918f6a4
adding riscv cycle counter
ct-clmsn Mar 5, 2024
97f3725
updated copyright in file to include authors
ct-clmsn Mar 5, 2024
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23 changes: 23 additions & 0 deletions kernel/cycle.h
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2003, 2007-14 Matteo Frigo
* Copyright (c) 2003, 2007-14 Massachusetts Institute of Technology
* Copyright (c) 2024 Christopher Taylor, Tactical Computing Labs, LLC
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MIT will require a copyright assignment to merge PRs like this.

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@ct-clmsn ct-clmsn Jul 18, 2024 •
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not a problem, can you send or post information on how that process works?

*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
Expand Down Expand Up @@ -562,3 +563,25 @@ static inline ticks getticks(void)
INLINE_ELAPSED(inline)
#define HAVE_TICK_COUNTER
#endif

/*----------------------------------------------------------------*/
/*
* RISC_V 64-bit cycle counter (RV64G)
*/
#if defined(__riscv) && (__riscv_xlen == 64) && !defined(HAVE_TICK_COUNTER)
typedef unsigned long ticks;

static __inline__ ticks getticks(void)
{
ticks ret;

__asm__ __volatile__ ("csrrs %0, 0xc00, x0" : "=r" (ret) );

/* no input, nothing else clobbered */
return ret;
}

INLINE_ELAPSED(inline)

#define HAVE_TICK_COUNTER
#endif