adding riscv cycle counter

[ct-clmsn]

adds riscv cycle counter support to fftw3

[rdolbeau]

The inclusion of the cycle counter (including support for rv32 in addition to rv64) is already part of the various RISC-V "V" efforts.

[ct-clmsn]

understood. this is a small fix and allows fftw3 to work on riscv processors that currently do not have vector hardware support. as of right now, the different riscv vector software support implementations are a block for using fftw3 on riscv.

[stevengj]

MIT will require a copyright assignment to merge PRs like this.

[ct-clmsn]

not a problem, can you send or post information on how that process works?

[rdolbeau]

I understand the urgency; but I don't think this implementation is satisfactory for upstreaming:
(a) no support for RV32
(b) hard-to-understand csrr when there is dedicated aliases like rdcycle and rdtime
(c) if this is using rdcycle, then user-land access was deprecated (security...) and will no longer be working Real Soon Now. Recent kernels on recent hardware have already dropped support (e.g. the manufacturer's kernel on the SpacemiT K1 SoC at least).

If there's some urgency, I would suggest merging separately the RISC-V version from here.

Edit: alternative proposed in #361