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drivers: flash: stm32g0: Implement APIs for option bytes and RDP #93159

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Merged
merged 2 commits into from
Oct 8, 2025
Merged

drivers: flash: stm32g0: Implement APIs for option bytes and RDP #93159

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1cbb0b0
drivers: flash: stm32g0: Implement option_bytes_write|read API
martinjaeger Jul 15, 2025
5c369b6
drivers: flash: stm32g0: Implement set|get_rdp_level API
martinjaeger Jul 15, 2025
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9 changes: 6 additions & 3 deletions drivers/flash/Kconfig.stm32
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Original file line number Diff line number Diff line change
Expand Up @@ -49,9 +49,12 @@ config FLASH_STM32_WRITE_PROTECT_DISABLE_PREVENTION

config FLASH_STM32_READOUT_PROTECTION
bool "Extended operation for flash readout protection control"
depends on SOC_SERIES_STM32F4X || SOC_SERIES_STM32L4X || \
SOC_SERIES_STM32G4X || SOC_SERIES_STM32F7X || \
SOC_SERIES_STM32H7X
depends on SOC_SERIES_STM32F4X || \
SOC_SERIES_STM32F7X || \
SOC_SERIES_STM32G0X || \
SOC_SERIES_STM32G4X || \
SOC_SERIES_STM32H7X || \
SOC_SERIES_STM32L4X
select FLASH_HAS_EX_OP
default n
help
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1 change: 1 addition & 0 deletions drivers/flash/flash_stm32_ex_op.c
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Expand Up @@ -331,6 +331,7 @@ int flash_stm32_ex_op(const struct device *dev, uint16_t code,
#if defined(CONFIG_FLASH_STM32_OPTION_BYTES) && ( \
defined(CONFIG_DT_HAS_ST_STM32F4_FLASH_CONTROLLER_ENABLED) || \
defined(CONFIG_DT_HAS_ST_STM32F7_FLASH_CONTROLLER_ENABLED) || \
defined(CONFIG_DT_HAS_ST_STM32G0_FLASH_CONTROLLER_ENABLED) || \
defined(CONFIG_DT_HAS_ST_STM32G4_FLASH_CONTROLLER_ENABLED) || \
defined(CONFIG_DT_HAS_ST_STM32L4_FLASH_CONTROLLER_ENABLED))
case FLASH_STM32_EX_OP_OPTB_READ:
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59 changes: 59 additions & 0 deletions drivers/flash/flash_stm32g0x.c
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Expand Up @@ -15,6 +15,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
#include <zephyr/device.h>
#include <string.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/sys/barrier.h>
#include <zephyr/init.h>
#include <soc.h>

Expand Down Expand Up @@ -195,6 +196,64 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
return rc;
}

int flash_stm32_option_bytes_write(const struct device *dev, uint32_t mask,
uint32_t value)
{
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
int rc;

if (regs->CR & FLASH_CR_OPTLOCK) {
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Should be if (regs->CR & FLASH_CR_OPTLOCK != 0) (despite other STM32 drivers don't do this).
Non-blocking comment.

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0U if we wanted to be pedantic 😉 (And I'd add parentheses to ensure no ambiguity about order of evaluation)

return -EIO;
}

if ((regs->OPTR & mask) == value) {
return 0;
}

rc = flash_stm32_wait_flash_idle(dev);
if (rc < 0) {
return rc;
}

regs->OPTR = (regs->OPTR & ~mask) | value;
regs->CR |= FLASH_CR_OPTSTRT;

/* Make sure previous write is completed. */
barrier_dsync_fence_full();

rc = flash_stm32_wait_flash_idle(dev);
if (rc < 0) {
return rc;
}

/* Force the option byte loading */
regs->CR |= FLASH_CR_OBL_LAUNCH;
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This may need to be adjusted based on the outcome of #91945.


return flash_stm32_wait_flash_idle(dev);
}

uint32_t flash_stm32_option_bytes_read(const struct device *dev)
{
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);

return regs->OPTR;
}

#if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
uint8_t flash_stm32_get_rdp_level(const struct device *dev)
{
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);

return (regs->OPTR & FLASH_OPTR_RDP_Msk) >> FLASH_OPTR_RDP_Pos;
}

void flash_stm32_set_rdp_level(const struct device *dev, uint8_t level)
{
flash_stm32_option_bytes_write(dev, FLASH_OPTR_RDP_Msk,
(uint32_t)level << FLASH_OPTR_RDP_Pos);
}
#endif /* CONFIG_FLASH_STM32_READOUT_PROTECTION */

/*
* The address space is always continuous, even though a subset of G0 SoCs has
* two flash banks.
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