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drivers: ethernet: phy: add driver for ksz9131 #90711
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drivers: ethernet: phy: add driver for ksz9131 #90711
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Add an entry to https://github.com/zephyrproject-rtos/zephyr/blob/main/tests/drivers/build_all/ethernet/app.overlay so it builds in CI. |
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@pdgendt An entry for ksz9131 added to |
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@TonyHan11 pls add PR description and address the things from sonarqube |
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@maass-hamburg updated with removing the unused property, renaming |
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@maass-hamburg
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Resolve the CI error by rebasing the commits (without changes). |
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| reg_val |= PHY_KSZ9131_ICS_LINK_UP_IE_MASK | PHY_KSZ9131_ICS_LINK_DOWN_IE_MASK; | ||
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| /* Write settings to Interrupt Control/Status register */ | ||
| ret = ksz9131_write(dev, 27, reg_val); |
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Use PHY_KSZ9131_ICS_REG macro instead of magic number
| goto done; | ||
| } | ||
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| gpio_init_callback(&data->gpio_callback, phy_mc_ksz8081_interrupt_handler, |
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| gpio_init_callback(&data->gpio_callback, phy_mc_ksz8081_interrupt_handler, | |
| ret = gpio_init_callback(&data->gpio_callback, phy_mc_ksz8081_interrupt_handler, |
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Hi @nandojve ,
Yes, we hope it be merged to v4.3. |
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I took a general look and LGTM!
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Ping @pdgendt , @maass-hamburg , @kartben . |
Add support for KSZ9131 (Gigabit Ethernet Transceiver with RGMII Support). As first starter, 100MBit/s mode is tested. https://www.microchip.com/en-us/product/ksz9131 Signed-off-by: Tony Han <[email protected]>
New lines are expected between PHY nodes by DevicetreeLinting. Signed-off-by: Tony Han <[email protected]>
Add build tests for Microchip KSZ9131. Signed-off-by: Tony Han <[email protected]>
Enable Link-Up and Link-Down interrupts. On the interrupt handling the monitor work is scheduled to update the link status and calling corresponding callback routine. Signed-off-by: Tony Han <[email protected]>
Read gigabit status from Master Slave Status Register. Signed-off-by: Tony Han <[email protected]>
Get the link state in the monitor and save it for get_link api implementation to use. Signed-off-by: Tony Han <[email protected]>
Add gmac1 and gmac1_mdio nodes. Signed-off-by: Tony Han <[email protected]>
Enable strong ordered access to the GMAC0 registers. Signed-off-by: Tony Han <[email protected]>
Configure the generic clocks to 125MHz for GMAC0. Signed-off-by: Tony Han <[email protected]>
Update to use the RGMII mode which is supported by SAMA7G54. Signed-off-by: Tony Han <[email protected]>
Remove extra new lines to satisfy the requirement of DevicetreeLinting. Signed-off-by: Tony Han <[email protected]>
Enable gmac0, gmac0_mdio and gmac0_phy nodes. Signed-off-by: Tony Han <[email protected]>
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This PR includes: