RA8x2 ethernet driver support

boards/renesas/ek_ra8d2/Kconfig.defconfig

@@ -0,0 +1,17 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_EK_RA8D2
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+endif # NETWORKING
+
+# Enable fixed clock for ethernet phy
+config CLOCK_CONTROL_FIXED_RATE_CLOCK
+	default y if ETH_PHY_DRIVER
+
+endif # BOARD_EK_RA8D2

boards/renesas/ek_ra8d2/ek_ra8d2-pinctrl.dtsi

@@ -162,4 +162,30 @@
 			drive-strength = "highspeed-high";
 		};
 	};
+
+	mdio1_default: mdio1_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_ETH_MII, 4, 15)>, /* MDC */
+				<RA_PSEL(RA_PSEL_ETH_MII, 4, 14)>; /* MDIO */
+			drive-strength = "medium";
+		};
+	};
+
+	eth1_default: eth1_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_ETH_RGMII, 3, 7)>, /* RGMII_TXD0 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 3, 6)>, /* RGMII_TXD1 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 3, 5)>, /* RGMII_TXD2 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 3, 4)>, /* RGMII_TXD3 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 3, 10)>, /* RGMII_TX_CTL */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 3, 9)>, /* RGMII_TX_CLK */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 9, 6)>, /* RGMII_RXD0 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 9, 7)>, /* RGMII_RXD1 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 9, 8)>, /* RGMII_RXD2 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 9, 9)>, /* RGMII_RXD3 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 2, 6)>, /* RGMII_RX_CTL */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 9, 5)>; /* RGMII_RX_CLK */
+			drive-strength = "high";
+		};
+	};
 };

boards/renesas/ek_ra8d2/ek_ra8d2.dtsi

@@ -88,6 +88,18 @@
 	};
 };
 
+/* In ek_ra8d2, phy chip use xtal as clock source
+ * so internal phy clock is not required.
+ */
+&clocks {
+	phyxtal: phy-xtal {
+		compatible = "fixed-clock";
+		clock-frequency = <DT_FREQ_M(25)>;
+		#clock-cells = <0x0>;
+		status = "okay";
+	};
+};
+
 &xtal {
 	clock-frequency = <DT_FREQ_M(24)>;
 	mosel = <0>;
@@ -147,6 +159,28 @@
 	status = "okay";
 };
 
+&eswclk {
+	clocks = <&pllp>;
+	div = <4>;
+	status = "okay";
+};
+
+&eswphyclk {
+	clocks = <&pllp>;
+	div = <2>;
+	status = "okay";
+};
+
+&ethphyclk {
+	clocks = <&pllr>;
+	div = <16>;
+	status = "okay";
+};
+
+&trng {
+	status = "okay";
+};
+
 &ioport0 {
 	status = "okay";
 };

boards/renesas/ek_ra8d2/ek_ra8d2_r7ka8d2kflcac_cm85.dts

@@ -21,6 +21,7 @@
 		zephyr,console = &uart8;
 		zephyr,shell-uart = &uart8;
 		zephyr,crc = &crc;
+		zephyr,entropy = &trng;
 	};
 
 	aliases {
@@ -211,3 +212,39 @@ arducam_ffc_40pin_i2c: &iic1 {};
 arducam_ffc_40pin_dvp_interface: &ceu {};
 
 arducam_ffc_40pin_dvp_xclk: &cam_clock {};
+
+&eswm {
+	interrupts = <27 1>;
+	interrupt-names = "gwdi";
+	status = "okay";
+};
+
+&eth1 {
+	phy-connection-type = "rgmii";
+	local-mac-address = [74 90 50 01 02 04];
+	phy-clock = <&phyxtal>;
+	phy-clock-type = "xtal";
+	phy-handle = <&phy0>;
+	pinctrl-0 = <&eth1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&mdio1 {
+	pinctrl-0 = <&mdio1_default>;
+	pinctrl-names = "default";
+	phy-connection-type = "rgmii";
+	status = "okay";
+
+	phy0: phy@0 {
+		compatible = "maxlinear,gpy111";
+		maxlinear,interface-type = "rgmii";
+		maxlinear,rx-internal-delay = "rx_skew_1n5";
+		reg = <0>;
+		int-gpios = <&ioport1 7 GPIO_ACTIVE_LOW>;
+		reset-gpios = <&ioport7 8 GPIO_ACTIVE_LOW>;
+		reset-assert-duration-us = <2000>;
+		reset-deassertion-timeout-ms = <300>;
+		status = "okay";
+	};
+};

boards/renesas/ek_ra8m2/Kconfig.defconfig

@@ -0,0 +1,27 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_EK_RA8M2
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+endif # NETWORKING
+
+# Enable fixed clock for ethernet phy
+config CLOCK_CONTROL_FIXED_RATE_CLOCK
+	default y if ETH_PHY_DRIVER
+
+if MDIO
+
+config MDIO_RENESAS_RA_RMAC_MDIO_HOLD_NS
+	default 4
+
+config MDIO_RENESAS_RA_RMAC_MDIO_CAPTURE_NS
+	default 4
+
+endif #MDIO
+
+endif # BOARD_EK_RA8M2

boards/renesas/ek_ra8m2/ek_ra8m2-pinctrl.dtsi

@@ -83,4 +83,30 @@
 			drive-strength = "high";
 		};
 	};
+
+	mdio0_default: mdio0_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_ETH_MII, 12, 11)>, /* MDC */
+				<RA_PSEL(RA_PSEL_ETH_MII, 12, 12)>; /* MDIO */
+			drive-strength = "medium";
+		};
+	};
+
+	eth0_default: eth0_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_ETH_RGMII, 11, 0)>, /* RGMII_TXD0 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 11, 2)>, /* RGMII_TXD1 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 11, 3)>, /* RGMII_TXD2 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 11, 4)>, /* RGMII_TXD3 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 7, 5)>, /* RGMII_TX_CTL */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 7, 6)>, /* RGMII_TX_CLK */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 7, 2)>, /* RGMII_RXD0 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 7, 1)>, /* RGMII_RXD1 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 7, 0)>, /* RGMII_RXD2 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 4, 6)>, /* RGMII_RXD3 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 4, 5)>, /* RGMII_RX_CTL */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 7, 3)>; /* RGMII_RX_CLK */
+			drive-strength = "high";
+		};
+	};
 };

boards/renesas/ek_ra8m2/ek_ra8m2.dtsi

@@ -76,6 +76,18 @@
 	};
 };
 
+/* In ek_ra8m2, phy chip use xtal as clock source
+ * so internal phy clock is not required.
+ */
+&clocks {
+	phyxtal: phy-xtal {
+		compatible = "fixed-clock";
+		clock-frequency = <DT_FREQ_M(25)>;
+		#clock-cells = <0x0>;
+		status = "okay";
+	};
+};
+
 &xtal {
 	clock-frequency = <DT_FREQ_M(24)>;
 	mosel = <0>;
@@ -135,6 +147,28 @@
 	status = "okay";
 };
 
+&eswclk {
+	clocks = <&pllp>;
+	div = <4>;
+	status = "okay";
+};
+
+&eswphyclk {
+	clocks = <&pllp>;
+	div = <2>;
+	status = "okay";
+};
+
+&ethphyclk {
+	clocks = <&pllr>;
+	div = <16>;
+	status = "okay";
+};
+
+&trng {
+	status = "okay";
+};
+
 &ioport0 {
 	status = "okay";
 };
@@ -151,6 +185,10 @@
 	status = "okay";
 };
 
+&ioport5 {
+	status = "okay";
+};
+
 &ioport6 {
 	status = "okay";
 };

boards/renesas/ek_ra8m2/ek_ra8m2_r7ka8m2jflcac_cm85.dts

@@ -21,6 +21,7 @@
 		zephyr,shell-uart = &uart8;
 		zephyr,canbus = &canfd1;
 		zephyr,crc = &crc;
+		zephyr,entropy = &trng;
 	};
 
 	aliases {
@@ -183,3 +184,39 @@
 mikrobus_serial: &uart7 {};
 
 mikrobus_spi: &spi1 {};
+
+&eswm {
+	interrupts = <29 1>;
+	interrupt-names = "gwdi";
+	status = "okay";
+};
+
+&eth0 {
+	phy-connection-type = "rgmii";
+	local-mac-address = [74 90 50 01 02 05];
+	phy-clock = <&phyxtal>;
+	phy-clock-type = "xtal";
+	phy-handle = <&phy0>;
+	pinctrl-0 = <&eth0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&mdio0 {
+	pinctrl-0 = <&mdio0_default>;
+	pinctrl-names = "default";
+	phy-connection-type = "rgmii";
+	status = "okay";
+
+	phy0: phy@0 {
+		compatible = "maxlinear,gpy111";
+		maxlinear,interface-type = "rgmii";
+		maxlinear,rx-internal-delay = "rx_skew_1n5";
+		reg = <0>;
+		int-gpios = <&ioportc 13 GPIO_ACTIVE_LOW>;
+		reset-gpios = <&ioport5 14 GPIO_ACTIVE_LOW>;
+		reset-assert-duration-us = <2000>;
+		reset-deassertion-timeout-ms = <300>;
+		status = "okay";
+	};
+};

boards/renesas/ek_ra8p1/Kconfig.defconfig

@@ -10,4 +10,15 @@ config SD_CMD_TIMEOUT
 
 endif # DISK_DRIVER_SDMMC
 
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+endif # NETWORKING
+
+# Enable fixed clock for ethernet phy
+config CLOCK_CONTROL_FIXED_RATE_CLOCK
+	default y if ETH_PHY_DRIVER
+
 endif # BOARD_EK_RA8P1

boards/renesas/ek_ra8p1/ek_ra8p1-pinctrl.dtsi

@@ -177,4 +177,30 @@
 			drive-strength = "highspeed-high";
 		};
 	};
+
+	mdio1_default: mdio1_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_ETH_MII, 4, 15)>, /* MDC */
+				<RA_PSEL(RA_PSEL_ETH_MII, 4, 14)>; /* MDIO */
+			drive-strength = "medium";
+		};
+	};
+
+	eth1_default: eth1_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_ETH_RGMII, 3, 7)>, /* RGMII_TXD0 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 3, 6)>, /* RGMII_TXD1 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 3, 5)>, /* RGMII_TXD2 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 3, 4)>, /* RGMII_TXD3 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 3, 10)>, /* RGMII_TX_CTL */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 3, 9)>, /* RGMII_TX_CLK */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 9, 6)>, /* RGMII_RXD0 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 9, 7)>, /* RGMII_RXD1 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 9, 8)>, /* RGMII_RXD2 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 9, 9)>, /* RGMII_RXD3 */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 2, 6)>, /* RGMII_RX_CTL */
+				<RA_PSEL(RA_PSEL_ETH_RGMII, 9, 5)>; /* RGMII_RX_CLK */
+			drive-strength = "high";
+		};
+	};
 };