STM32F2/F4/F7 PLL clock rework #100757
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STM32F2/F4/F7 PLL clock rework #100757
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… PLLs STM32F2, F4 and F7 have up to 3 PLLs: PLL, PLLI2S and PLLSAI. These PLLs are very similar, the principal differences are which outputs are available for which PLL of each SoC. Instead of having a large number of files to describe all the possible very similar variants, use one single binding to rule them all. Signed-off-by: Guillaume Gautier <[email protected]>
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dts/arm/st/f4/stm32f412.dtsi
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| plli2s: plli2s { | ||
| #clock-cells = <0>; | ||
| compatible = "st,stm32f411-plli2s-clock"; | ||
| compatible = "st,stm32fx-plli2s-clock"; |
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| compatible = "st,stm32fx-plli2s-clock"; | |
| compatible = "st,stm32fx-pll-clock"; |
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Oops, I missed that one. Fixed.
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| #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32fx_pll_clock, okay) && \ | ||
| DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32fx_pll_clock, okay) |
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Simplify to
#if defined(DT_PLL_CLOCKS_CTRL) && defined(DT_PLLI2S_CLOCKS_CTRL)
?
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Good idea, much less verbose. Done
| "For the PLLSAI, both div-r and div-divr must be present if one of them is present"); | ||
| #endif /* STM32_PLLSAI_ENABLED && RCC_PLLSAICFGR_PLLSAIR */ | ||
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| #if STM32_PLL_ENABLED |
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| #if STM32_PLL_ENABLED | |
| #ifdef STM32_PLL_ENABLED |
STM32_PLL_ENABLED is either not defined or defined to 1.
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If not defined, I think the preprocessor consider it as 0. But I reverted back to ifdef all the same.
| } | ||
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| #if defined(STM32_CK48_ENABLED) | ||
| #if STM32_CK48_ENABLED |
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Restore the previous way: STM32_CK48_ENABLED is either not defined or defined to 1.
| #endif /* defined(STM32_PLL_ENABLED) */ | ||
| #endif /* STM32_PLL_ENABLED */ | ||
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| #if STM32_PLLI2S_ENABLED |
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| #if STM32_PLLI2S_ENABLED | |
| #ifdef STM32_PLLI2S_ENABLED |
| #endif /* STM32_PLLI2S_ENABLED */ | ||
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| #if defined(STM32_PLLSAI_ENABLED) | ||
| #if STM32_PLLSAI_ENABLED |
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| #if STM32_PLLSAI_ENABLED | |
| #ifdef STM32_PLLSAI_ENABLED |
For all STM32F2, F4 and F7, use the new binding instead of the various ones previously defined. For F411 and F446, this removes the need to define the PLLI2S since it is already included in F401. For F7, this commit also adds the PLLI2S that was missing. Signed-off-by: Guillaume Gautier <[email protected]>
Add some missing clock sources and reorganize them to class the PLL outputs together. Signed-off-by: Guillaume Gautier <[email protected]>
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This commit updates the STM32Fx clock driver to add complete support for all PLLs for all SoCs. Supports all outputs and additional divisors: - PLL-DIV-R - PLLI2S-P - PLLI2S-DIV-Q - PLLI2S-DIV-R Adds global checks to make sure that all: - All PLLs share the same source clocks - All PLLs share the same M-Divisor (on applicable SoCs) - Both div-X and div-divX are defined (on applicable SoCs) Functions get_plli2s_source and get_plli2ssrc_frequency are added to make sure that PLLI2S can be used even if PLL is not defined. Signed-off-by: Guillaume Gautier <[email protected]>
With the new PLL bindings, fixes a few board dts and overlays that are missing some properties. Signed-off-by: Guillaume Gautier <[email protected]>
Rename CLK48M_SEL to CK48M_SEL for consistency with stm32f410_clock.h. Signed-off-by: Guillaume Gautier <[email protected]>
Move get_ck48_frequency function outside of the #if STM32_PLL_ENABLED because it should be usable even if the main PLL is not used. The mux can indeed be used with PLLI2S. Signed-off-by: Guillaume Gautier <[email protected]>
On STM32F446, F469, F479 and on STM32F7x, the CK48M mux can have either PLL Q or PLLSAI P as input. Adds the support for the PLLSAI P input in the driver. Signed-off-by: Guillaume Gautier <[email protected]>
For STM32F446, F469, F479 and F7x, add the clk48 node in the dtsi. This allows configuring the clock source of the CLK48 clock. It is necessary to add it for the SDIO peripheral that can have either SYSCLK or CLK48 as clock source. Signed-off-by: Guillaume Gautier <[email protected]>
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This PR replaces all PLL bindings for STM32F2/F4/F7 by a single one, and adds support for missing PLL outputs for some PLLs of some SoCs.
Here is the table I used as reference, extracted from the information from the different RefMans. A * indicates the presence of an additional divisor for this PLL output.
With this PR, all these PLL outputs are now supported, including with the additional divisors. Checks are in place to verify all enabled share the same source, that the div-M is the same between active PLLs (for those SoCs that don't have individual div-M), and that additional divisors are correctly defined if they are available and the output is used.
It also completes the support of the 48M clock for some SoCs.