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Add pit feature for mcxe31x #100752

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bed0d43
drivers: clock_control_nxp_mc_cgm.c: update clock driver
lucien-nxp Dec 3, 2025
a12ac0c
boards： nxp: frdm_mcxe31b: add pit support
lucien-nxp Dec 9, 2025
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4 changes: 4 additions & 0 deletions boards/nxp/frdm_mcxe31b/frdm_mcxe31b.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -159,6 +159,10 @@
overdrive = <12>;
};

&pit_0 {
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@yvesll yvesll Dec 10, 2025

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As pit is an optional counter, is it necessary to enable it on board level without any channel enabled?

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@lucien-nxp lucien-nxp Dec 12, 2025

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I think board level only enable instances, and set some specific parameter for this instance in specific application code(except if some common setting for this instances). Channel settings should be put into application level should be better because this should be determined by application code.

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@yvesll yvesll Dec 17, 2025 •
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The board dts guide has been updated since I last viewed, need a confirm #99759 (comment)
Anyway, it's a tiny improvement and will not block this pr.

status = "okay";
};

&pll {
status = "okay";
workmode = "Integer";
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47 changes: 28 additions & 19 deletions drivers/clock_control/clock_control_nxp_mc_cgm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -42,8 +42,10 @@

static int mc_cgm_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
{
uint32_t clock_name = (uint32_t)sub_system;

switch (clock_name) {

Check warning on line 47 in drivers/clock_control/clock_control_nxp_mc_cgm.c

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SonarQubeCloud / SonarCloud Code Analysis

Reduce the number of switch cases from 36 to at most 30. 


See more on https://sonarcloud.io/project/issues?id=zephyrproject-rtos_zephyr&issues=AZsDtF4e8VmGjMV8mIeM&open=AZsDtF4e8VmGjMV8mIeM&pullRequest=100752
#if defined(CONFIG_CAN_MCUX_FLEXCAN)
switch ((uint32_t)sub_system) {
case MCUX_FLEXCAN0_CLK:
CLOCK_EnableClock(kCLOCK_Flexcan0);
break;
Expand All @@ -62,13 +64,9 @@
case MCUX_FLEXCAN5_CLK:
CLOCK_EnableClock(kCLOCK_Flexcan5);
break;
default:
break;
}
#endif /* defined(CONFIG_CAN_MCUX_MCAN) */

#if defined(CONFIG_UART_MCUX_LPUART)
switch ((uint32_t)sub_system) {
case MCUX_LPUART0_CLK:
CLOCK_EnableClock(kCLOCK_Lpuart0);
break;
Expand Down Expand Up @@ -117,13 +115,9 @@
case MCUX_LPUART15_CLK:
CLOCK_EnableClock(kCLOCK_Lpuart15);
break;
default:
break;
}
#endif /* defined(CONFIG_UART_MCUX_LPUART) */

#if defined(CONFIG_SPI_NXP_LPSPI)
switch ((uint32_t)sub_system) {
case MCUX_LPSPI0_CLK:
CLOCK_EnableClock(kCLOCK_Lpspi0);
break;
Expand All @@ -142,36 +136,40 @@
case MCUX_LPSPI5_CLK:
CLOCK_EnableClock(kCLOCK_Lpspi5);
break;
default:
break;
}
#endif /* defined(CONFIG_SPI_NXP_LPSPI) */

#if defined(CONFIG_I2C_MCUX_LPI2C)
switch ((uint32_t)sub_system) {
case MCUX_LPI2C0_CLK:
CLOCK_EnableClock(kCLOCK_Lpi2c0);
break;
case MCUX_LPI2C1_CLK:
CLOCK_EnableClock(kCLOCK_Lpi2c1);
break;
default:
break;
}
#endif /* defined(CONFIG_I2C_MCUX_LPI2C) */

#if defined(CONFIG_COUNTER_MCUX_STM)
switch ((uint32_t)sub_system) {
case MCUX_STM0_CLK:
CLOCK_EnableClock(kCLOCK_Stm0);
break;
case MCUX_STM1_CLK:
CLOCK_EnableClock(kCLOCK_Stm1);
break;
default:
#endif /* defined(CONFIG_COUNTER_MCUX_STM) */

#ifdef CONFIG_COUNTER_NXP_PIT
case MCUX_PIT0_CLK:
CLOCK_EnableClock(kCLOCK_Pit0Clk);
break;
case MCUX_PIT1_CLK:
CLOCK_EnableClock(kCLOCK_Pit1Clk);
break;
case MCUX_PIT2_CLK:
CLOCK_EnableClock(kCLOCK_Pit2Clk);
break;
#endif
default:
return -ENOTSUP;
}
#endif /* defined(CONFIG_COUNTER_MCUX_STM) */

return 0;
}
Expand Down Expand Up @@ -262,6 +260,17 @@
*rate = CLOCK_GetStmClkFreq(1);
break;
#endif /* defined(CONFIG_COUNTER_MCUX_STM) */

#if defined(CONFIG_COUNTER_NXP_PIT)
case MCUX_PIT0_CLK:
case MCUX_PIT1_CLK:
case MCUX_PIT2_CLK:
*rate = CLOCK_GetAipsSlowClkFreq();
break;
#endif /* defined(CONFIG_COUNTER_NXP_PIT) */

default:
return -ENOTSUP;
}
return 0;
}
Expand Down
78 changes: 78 additions & 0 deletions dts/arm/nxp/nxp_mcxe31x_common.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -709,6 +709,32 @@
clocks = <&mc_cgm MCUX_PIT0_CLK>;
max-load-value = <0xffffffff>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;

pit_0_channel0: pit_0_channel@0 {
compatible = "nxp,pit-channel";
reg = <0>;
status = "disabled";
};

pit_0_channel1: pit_0_channel@1 {
compatible = "nxp,pit-channel";
reg = <1>;
status = "disabled";
};

pit_0_channel2: pit_0_channel@2 {
compatible = "nxp,pit-channel";
reg = <2>;
status = "disabled";
};

pit_0_channel3: pit_0_channel@3 {
compatible = "nxp,pit-channel";
reg = <3>;
status = "disabled";
};
};

pit_1: pit@b4000 {
Expand All @@ -718,6 +744,32 @@
clocks = <&mc_cgm MCUX_PIT1_CLK>;
max-load-value = <0xffffffff>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;

pit_1_channel0: pit_1_channel@0 {
compatible = "nxp,pit-channel";
reg = <0>;
status = "disabled";
};

pit_1_channel1: pit_1_channel@1 {
compatible = "nxp,pit-channel";
reg = <1>;
status = "disabled";
};

pit_1_channel2: pit_1_channel@2 {
compatible = "nxp,pit-channel";
reg = <2>;
status = "disabled";
};

pit_1_channel3: pit_1_channel@3 {
compatible = "nxp,pit-channel";
reg = <3>;
status = "disabled";
};
};

pit_2: pit@2fc000 {
Expand All @@ -727,6 +779,32 @@
clocks = <&mc_cgm MCUX_PIT2_CLK>;
max-load-value = <0xffffffff>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;

pit_2_channel0: pit_2_channel@0 {
compatible = "nxp,pit-channel";
reg = <0>;
status = "disabled";
};

pit_2_channel1: pit_2_channel@1 {
compatible = "nxp,pit-channel";
reg = <1>;
status = "disabled";
};

pit_2_channel2: pit_2_channel@2 {
compatible = "nxp,pit-channel";
reg = <2>;
status = "disabled";
};

pit_2_channel3: pit_2_channel@3 {
compatible = "nxp,pit-channel";
reg = <3>;
status = "disabled";
};
};

pll: plldig@402e0000 {
Expand Down
3 changes: 2 additions & 1 deletion include/zephyr/dt-bindings/clock/nxp_mc_cgm.h
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,8 @@
/* Note- clock identifiers in this file must be unique,
* as the driver uses them in a switch case
*/

#define MCUX_MC_CGM_PERIPHERAL_MASK 0xFF00UL
#define MCUX_MC_CGM_INSTANCE_MASK 0xFFUL
#define MCUX_MC_CGM_CLK_ID(high, low) ((high << 8) | (low))

/* These IDs are used within SOC macros, and thus cannot be defined
Expand Down
21 changes: 21 additions & 0 deletions tests/drivers/counter/counter_basic_api/boards/frdm_mcxe31b.overlay
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Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/

&pit_0_channel0 {
status = "okay";
};

&pit_0_channel1 {
status = "okay";
};

&pit_0_channel2 {
status = "okay";
};

&pit_0_channel3 {
status = "okay";
};
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