Popular repositories Loading

1. Network-on-Chip-Verilog Network-on-Chip-Verilog Public

   A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.

   VHDL 6

2. thinpad thinpad Public

   A 5-stage pipelined CPU in SystemVerilog which supports interrupts and exceptions, also support uCore (an OS written in C++), major project of Principle of Computer Organizations

   Verilog 1

3. Minidecaf Minidecaf Public

   A compiler for a subset of C language, target environment: RISCV, implemented in Python, major project of Compiler Principles, Tsinghua University, 2021 Fall.

   Python 1

4. recovery-test recovery-test Public

   C++

5. wordle-rust wordle-rust Public

   Wordle game in Rust, major project for Rust Course in Tsinghua University.

   Rust

6. rCore-Tutorial-Code-2023S rCore-Tutorial-Code-2023S Public template

   Forked from LearningOS/rCore-Tutorial-Code-2023S

   My implementation of rCore. Check each branch for details!