Add missing batch cast from rvv types

xtensor-stack · Jan 15, 2025 · 68cd020 · 68cd020
1 parent e28ef98
commit 68cd020
Showing 1 changed file with 40 additions and 0 deletions.
diff --git a/include/xsimd/types/xsimd_rvv_register.hpp b/include/xsimd/types/xsimd_rvv_register.hpp
@@ -143,6 +143,27 @@ namespace xsimd
                 return __riscv_vreinterpret_i8m1(x);
             }
             template <>
+            XSIMD_INLINE rvv_type_info<int16_t, rvv_width_m1 * 1>::type
+            rvv_type_info<int16_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
+                __rvv_uint8m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_i16m1(x);
+            }
+            template <>
+            XSIMD_INLINE rvv_type_info<int32_t, rvv_width_m1 * 1>::type
+            rvv_type_info<int32_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
+                __rvv_uint8m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_i32m1(x);
+            }
+            template <>
+            XSIMD_INLINE rvv_type_info<int64_t, rvv_width_m1 * 1>::type
+            rvv_type_info<int64_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
+                __rvv_uint8m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_i64m1(x);
+            }
+            template <>
             XSIMD_INLINE rvv_type_info<uint16_t, rvv_width_m1 * 1>::type
             rvv_type_info<uint16_t, rvv_width_m1 * 1>::bitcast<__rvv_uint8m1_t>(
                 __rvv_uint8m1_t x) noexcept
@@ -179,6 +200,25 @@ namespace xsimd
                 return __riscv_vreinterpret_u8m1(x);
             }
 
+            template <>
+            XSIMD_INLINE rvv_type_info<int16_t, rvv_width_m1 * 1>::byte_type
+            rvv_type_info<int16_t, rvv_width_m1 * 1>::as_bytes<__rvv_int16m1_t>(__rvv_int16m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_u8m1(x);
+            }
+            template <>
+            XSIMD_INLINE rvv_type_info<int32_t, rvv_width_m1 * 1>::byte_type
+            rvv_type_info<int32_t, rvv_width_m1 * 1>::as_bytes<__rvv_int32m1_t>(__rvv_int32m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_u8m1(x);
+            }
+            template <>
+            XSIMD_INLINE rvv_type_info<int64_t, rvv_width_m1 * 1>::byte_type
+            rvv_type_info<int64_t, rvv_width_m1 * 1>::as_bytes<__rvv_int64m1_t>(__rvv_int64m1_t x) noexcept
+            {
+                return __riscv_vreinterpret_u8m1(x);
+            }
+
             template <>
             XSIMD_INLINE rvv_type_info<uint8_t, rvv_width_m1 * 1>::byte_type
             rvv_type_info<uint8_t, rvv_width_m1 * 1>::as_bytes<__rvv_uint8m1_t>(__rvv_uint8m1_t x) noexcept