Fix missing images & typos; remove redundant image

Exercises/assignment3.md

@@ -2,7 +2,7 @@
 
 In this assignment, you will add a next line prefetcher in the memory system. 
 
-![](figs/assignment3_fig1.png)
+![](../figs/assignment3_fig1.png)
 
 * The `LSU` unit takes a vector of addresses. It also includes status bits like read and valid bit for each of the threads. The `LSU` unit starts with an adder that adds the offset to each of the base addresses and computes the address of load/store. 
 
@@ -15,9 +15,9 @@ The processor generates memory addresses and inserts the new memory address into
 `VX_pipe_register`. Since `VX_pipe_register` takes only one memory request at a time, we need to insert a mux to choose between demand memory request and prefetch request. 
 The VX pipe register takes the input and outputs it in the next cycle. The output of the `VX_pipe_register` is then fed to the index buffer and sent to the cache. This makes sure the output changes only at clock edges. 
 
-![](figs/assignment3_fig2.png)
+![](../figs/assignment3_fig2.png)
 
-![](figs/assignment3_fig3.png)
+![](../figs/assignment3_fig3.png)
 
 The `stall_in` signal acts as an enable for the pipe register. `stall_in` checks that there is a valid request and that we are ready(the cache is not busy) to push that request into the pipe register. When both these conditions are met, we enable input into the pipe register. 
 

Solutions/assignment3_solution.md

@@ -18,14 +18,14 @@ make
 
 ### Step 1: Insert addr+4 into `req_pipe_reg` for pre_fetch load.
 
-For background knowledge of `handsake`, please see this [link](http://fpgacpu.ca/fpga/handshake.html).
+For background knowledge of `handshake`, please see this [link](http://fpgacpu.ca/fpga/handshake.html).
 Without prefetch, a whole process of a normal load request is as following:
 
-1. VX_issue provides `full_addr` and set `valid bit` to 1. VX_issue will keep holding `full_addr` until handsake has done.
+1. VX_issue provides `full_addr` and set `valid bit` to 1. VX_issue will keep holding `full_addr` until handshake has done.
 2. VX_lsu_unit will set `ready bit` to 1 as long as it's ready to execute new instruction.
-3. At the cycle when both `valid bit` and `ready bit` are 1, handsake is done, VX_issue will move to next instructions, and VX_lsu_unit accepts the `full_addr`, store this address into `req_pipe_reg`, and executes load/store accordingly.
+3. At the cycle when both `valid bit` and `ready bit` are 1, handshake is done, VX_issue will move to next instructions, and VX_lsu_unit accepts the `full_addr`, store this address into `req_pipe_reg`, and executes load/store accordingly.
 
-When there is a prefetch, after the handsake has done, we have to provide a new request to VX_lsu_unit for the prefetch and insert it into `req_pipe_reg`. For detailed information, please see [source code](https://github.com/vortexgpgpu/vortex/pull/22/files#diff-e7c7dffbfe7b26e92b9b1675965b8920f4acaf6c337f1a53d837738231898465R57).
+When there is a prefetch, after the handshake has done, we have to provide a new request to VX_lsu_unit for the prefetch and insert it into `req_pipe_reg`. For detailed information, please see [source code](https://github.com/vortexgpgpu/vortex/pull/22/files#diff-e7c7dffbfe7b26e92b9b1675965b8920f4acaf6c337f1a53d837738231898465R57).
 
 ### Step 2: Add prefetch information into metadata.