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[DeepSeek][ROCm] V4.1-Flash: enable sparse-MLA Gluon kernel + MXFP4 sparse indexer on MI355X - #1049
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Code Review
This pull request updates the metadata date and adds the VLLM_ROCM_USE_AITER_TRITON_SPARSE_MLA environment variable to enable ROCm sparse-MLA kernel optimizations. The reviewer suggests moving this environment variable from the strategy-specific overrides to the top-level hardware overrides block to ensure the optimization is applied across all compatible serving strategies on MI355X hardware.
| extra_env: | ||
| # Aiter's Gluon sparse-MLA kernel (vllm-project/vllm#53492), gfx950 | ||
| # only. Validated on DSv4.1-Flash at TP4/MI355X in that PR: faster | ||
| # prefill and decode with unchanged GSM8K accuracy. | ||
| VLLM_ROCM_USE_AITER_TRITON_SPARSE_MLA: "1" |
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The environment variable VLLM_ROCM_USE_AITER_TRITON_SPARSE_MLA: "1" is a hardware-specific optimization for gfx950 (MI355X) and is independent of the serving strategy. Currently, it is defined under strategy_overrides.single_node_tp.hardware_overrides.mi355x, which means it will only be applied when using the single_node_tp strategy. To ensure this optimization is applied across all compatible strategies (such as multi_node_tp or pd_cluster) when running on mi355x, it should be moved to the top-level hardware_overrides.mi355x block instead.
…parse indexer on MI355X Add to the MI355X TP override: - VLLM_ROCM_USE_AITER_TRITON_SPARSE_MLA=1 for vllm-project/vllm#53492's gfx950-only Gluon sparse-MLA kernel. - --attention-config '{"indexer_kv_dtype":"mxfp4","indexer_sparse_logits":true}' for vllm-project/vllm#58671's ROCm paged MXFP4 sparse indexer, replacing the dense fp8 indexer path. - --block-size 128, which the fp4 indexer and SparseMLA backend prefer once active (auto-resolution otherwise falls back to 64). Both vLLM PRs are merged and gfx950-scoped. Mirrors SemiAnalysisAI/InferenceX#3555 and SemiAnalysisAI/InferenceX#3571. Signed-off-by: fai <fangzhouai@gmail.com> Co-authored-by: Cursor <cursoragent@cursor.com>
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Address review feedback: the GPU-validation paragraph still named the superseded nightly-rocm100-29468dde pin. Point it at nightly-rocm100-ac9126e5 and run 36824408313 (TP4 and TP2, concurrency 1-64; eval-only TP4 c64 GSM8K 0.9712 strict / 0.9704 flexible), list the earlier sweeps as superseded, and cite the merged upstream recipe vllm-project/recipes#1049. The English and Chinese pages change together. 中文:根据评审意见,GPU 验证段落仍写着已被取代的 nightly-rocm100-29468dde。 现改为 nightly-rocm100-ac9126e5 与运行 36824408313(TP4 与 TP2,并发 1-64; 仅评测的 TP4 c64 GSM8K 为 strict 0.9712 / flexible 0.9704),将此前的 sweep 标注为已被取代,并引用已合并的上游配方 vllm-project/recipes#1049。中英文页面 同步更新。 Co-authored-by: Cursor <cursoragent@cursor.com>
…er / DSv4.1-Flash vLLM:启用 ROCm 分页 MXFP4 稀疏 indexer (#3571) * Repin DSv4.1-Flash MI355X vLLM AgentX to nightly-rocm100-ac9126e5 (includes #58671) Enables vllm-project/vllm#58671's ROCm paged MXFP4 sparse-logits indexer via --attention-config and --block-size 128, replacing the dense fp8 indexer path. A live A/B test (TP2 c16, matched 900s window) measured #58671 giving +14.7/+14.9% p50/p90 interactivity and -9.5/-10.8% p50/p90 e2e latency over the dense path, with throughput/GPU unchanged. Also drops c128 from both TP2 and TP4 conc-lists for this recipe. Co-authored-by: Cursor <cursoragent@cursor.com> * Repin DSv4.1-Flash MI355X vLLM AgentX to nightly-rocm100-ac9126e5 (includes #58671) Enables vllm-project/vllm#58671's ROCm paged MXFP4 sparse-logits indexer via --attention-config and --block-size 128, replacing the dense fp8 indexer path. A live A/B test (TP2 c16, matched 900s window) measured #58671 giving +14.7/+14.9% p50/p90 interactivity and -9.5/-10.8% p50/p90 e2e latency over the dense path, with throughput/GPU unchanged. Also drops c128 from both TP2 and TP4 conc-lists for this recipe. Co-authored-by: Cursor <cursoragent@cursor.com> * fix(dsv41flash): align MI355X vLLM changelog and docs with the recipe - perf-changelog: make the new entry English-only, as AGENTS.md now requires; record VLLM_ROCM_USE_AITER_TRITON_SPARSE_MLA=True, which this PR also sets; state why c128 is dropped; spell out the vLLM PR references. - amd-master.yaml and configuration-procedures (EN and ZH): replace the remaining c128 statements with the current c1-c64 range. No recipe or master-config value changes. 中文: - perf-changelog:按 AGENTS.md 的最新要求将新条目改为仅英文;记录本 PR 同时设置的 VLLM_ROCM_USE_AITER_TRITON_SPARSE_MLA=True;说明移除 c128 的原因;写全 vLLM PR 引用。 - amd-master.yaml 与 configuration-procedures(中英文):将残留的 c128 描述更新为当前的 c1-c64 范围。 配方与主配置的取值均无变化。 Co-authored-by: Cursor <cursoragent@cursor.com> * docs(dsv41flash): update MI355X GPU validation for the ac9126e5 pin Address review feedback: the GPU-validation paragraph still named the superseded nightly-rocm100-29468dde pin. Point it at nightly-rocm100-ac9126e5 and run 36824408313 (TP4 and TP2, concurrency 1-64; eval-only TP4 c64 GSM8K 0.9712 strict / 0.9704 flexible), list the earlier sweeps as superseded, and cite the merged upstream recipe vllm-project/recipes#1049. The English and Chinese pages change together. 中文:根据评审意见,GPU 验证段落仍写着已被取代的 nightly-rocm100-29468dde。 现改为 nightly-rocm100-ac9126e5 与运行 36824408313(TP4 与 TP2,并发 1-64; 仅评测的 TP4 c64 GSM8K 为 strict 0.9712 / flexible 0.9704),将此前的 sweep 标注为已被取代,并引用已合并的上游配方 vllm-project/recipes#1049。中英文页面 同步更新。 Co-authored-by: Cursor <cursoragent@cursor.com> --------- Co-authored-by: Cursor <cursoragent@cursor.com> Co-authored-by: Chun Fang <chun.fang@amd.com>
Purpose
Add to the MI355X
single_node_tpoverride inDeepSeek-V4.1-Flash.yaml:VLLM_ROCM_USE_AITER_TRITON_SPARSE_MLA: "1"— forcesvllm-project/vllm#53492's
gfx950-only AITER Gluon sparse-MLA kernel. That PR's own test plan
validates it on DSv4.1-Flash at TP4/MI355X: faster prefill/decode
TTFT/TPOT than the default Triton sparse-MLA path, unchanged GSM8K
accuracy.
--attention-config '{"indexer_kv_dtype":"mxfp4","indexer_sparse_logits":true}'— enables vllm-project/vllm#58671's
ROCm paged MXFP4 sparse-logits indexer kernel, replacing the dense fp8
indexer path.
--block-size 128— the fp4 indexer and SparseMLA backend prefer thisonce active; vLLM's block-size auto-resolution otherwise falls back to
64, the smallest size any of this model's 4+ attention backends merely
supports.
Both vLLM PRs are merged and gfx950-scoped. This mirrors
SemiAnalysisAI/InferenceX#3555
(sparse-MLA env var) and
SemiAnalysisAI/InferenceX#3571
(mxfp4 indexer + block-size), so the recipe and the InferenceX benchmark
config agree on MI355X.
Scoped to
mi355xonly — the sharedhardware_overrides.amdblock alsocovers MI325X (gfx942), which doesn't have this kernel support, and this
file has no MI350X-specific override today; I have no MI350X validation of
my own to add one.
Duplicate-work check
Searched open/closed PRs and issues on this repo for
VLLM_ROCM_USE_AITER_TRITON_SPARSE_MLA,indexer_kv_dtype,mxfp4 indexer,block-size 128, andDeepSeek-V4.1-Flash mi355x. No existing PR adds theseto this recipe. PR #962 (same author, open) touches the same file but a
disjoint, older section (image pin +
--moe-backend) predating the currentfile structure.
Test Plan
Test Result
No new warnings or errors versus a clean
mainrun of the same script.AI assistance disclosure
Investigated with Claude Sonnet 5 (Cursor): confirmed vLLM PRs #53492 and
#58671 are merged and gfx950-scoped, pulled their DSv4.1-Flash/MI355X
validation numbers, cross-checked against the two InferenceX PRs, and ran
this repo's own YAML validator. I reviewed the diff and am responsible for
it.