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PR for tstellar/llvm-project#929 #930

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12 changes: 6 additions & 6 deletions llvm/include/llvm/CodeGen/TargetInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -269,7 +269,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
virtual Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
return 0;
}
Expand All @@ -278,7 +278,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// bytes loaded from the stack. This must be implemented if a backend
/// supports partial stack slot spills/loads to further disambiguate
/// what the load does.
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
virtual Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex,
unsigned &MemBytes) const {
MemBytes = 0;
Expand All @@ -287,7 +287,7 @@ class TargetInstrInfo : public MCInstrInfo {

/// Check for post-frame ptr elimination stack locations as well.
/// This uses a heuristic so it isn't reliable for correctness.
virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
virtual Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
int &FrameIndex) const {
return 0;
}
Expand All @@ -307,7 +307,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
virtual Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
return 0;
}
Expand All @@ -316,7 +316,7 @@ class TargetInstrInfo : public MCInstrInfo {
/// bytes stored to the stack. This must be implemented if a backend
/// supports partial stack slot spills/loads to further disambiguate
/// what the store does.
virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
virtual Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex,
unsigned &MemBytes) const {
MemBytes = 0;
Expand All @@ -325,7 +325,7 @@ class TargetInstrInfo : public MCInstrInfo {

/// Check for post-frame ptr elimination stack locations as well.
/// This uses a heuristic, so it isn't reliable for correctness.
virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
virtual Register isStoreToStackSlotPostFE(const MachineInstr &MI,
int &FrameIndex) const {
return 0;
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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Expand Up @@ -2186,7 +2186,7 @@ bool AArch64InstrInfo::isFPRCopy(const MachineInstr &MI) {
return false;
}

unsigned AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
switch (MI.getOpcode()) {
default:
Expand All @@ -2210,7 +2210,7 @@ unsigned AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
return 0;
}

unsigned AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
switch (MI.getOpcode()) {
default:
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.h
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Expand Up @@ -56,9 +56,9 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
const MachineInstr &MIb) const override;

unsigned isLoadFromStackSlot(const MachineInstr &MI,
Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
unsigned isStoreToStackSlot(const MachineInstr &MI,
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

/// Does this instruction set its full destination register to zero?
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -8526,7 +8526,7 @@ unsigned SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,
return getNamedOperand(MI, AMDGPU::OpName::data)->getReg();
}

unsigned SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
Register SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
if (!MI.mayLoad())
return Register();
Expand All @@ -8540,7 +8540,7 @@ unsigned SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
return Register();
}

unsigned SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Register SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
if (!MI.mayStore())
return Register();
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.h
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Expand Up @@ -1205,9 +1205,9 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;

unsigned isLoadFromStackSlot(const MachineInstr &MI,
Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
unsigned isStoreToStackSlot(const MachineInstr &MI,
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

unsigned getInstBundleSize(const MachineInstr &MI) const;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARC/ARCInstrInfo.cpp
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Expand Up @@ -65,7 +65,7 @@ static bool isStore(int Opcode) {
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
unsigned ARCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
Register ARCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
int Opcode = MI.getOpcode();
if (isLoad(Opcode)) {
Expand All @@ -84,7 +84,7 @@ unsigned ARCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
unsigned ARCInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Register ARCInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
int Opcode = MI.getOpcode();
if (isStore(Opcode)) {
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARC/ARCInstrInfo.h
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Expand Up @@ -37,15 +37,15 @@ class ARCInstrInfo : public ARCGenInstrInfo {
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
unsigned isLoadFromStackSlot(const MachineInstr &MI,
Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

/// If the specified machine instruction is a direct
/// store to a stack slot, return the virtual or physical register number of
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
unsigned isStoreToStackSlot(const MachineInstr &MI,
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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Expand Up @@ -1304,7 +1304,7 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
}
}

unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Register ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
switch (MI.getOpcode()) {
default: break;
Expand Down Expand Up @@ -1356,7 +1356,7 @@ unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
return 0;
}

unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
Register ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
int &FrameIndex) const {
SmallVector<const MachineMemOperand *, 1> Accesses;
if (MI.mayStore() && hasStoreToStackSlot(MI, Accesses) &&
Expand Down Expand Up @@ -1555,7 +1555,7 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
}
}

unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
Register ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
switch (MI.getOpcode()) {
default: break;
Expand Down Expand Up @@ -1613,7 +1613,7 @@ unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
return 0;
}

unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
Register ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
int &FrameIndex) const {
SmallVector<const MachineMemOperand *, 1> Accesses;
if (MI.mayLoad() && hasLoadFromStackSlot(MI, Accesses) &&
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/ARM/ARMBaseInstrInfo.h
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Expand Up @@ -186,13 +186,13 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
///
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;

unsigned isLoadFromStackSlot(const MachineInstr &MI,
Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
unsigned isStoreToStackSlot(const MachineInstr &MI,
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
int &FrameIndex) const override;
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
Register isStoreToStackSlotPostFE(const MachineInstr &MI,
int &FrameIndex) const override;

void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AVR/AVRInstrInfo.cpp
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Expand Up @@ -91,7 +91,7 @@ void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
}

unsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
Register AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
switch (MI.getOpcode()) {
case AVR::LDDRdPtrQ:
Expand All @@ -110,7 +110,7 @@ unsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
return 0;
}

unsigned AVRInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Register AVRInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
switch (MI.getOpcode()) {
case AVR::STDPtrQRr:
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AVR/AVRInstrInfo.h
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Expand Up @@ -87,9 +87,9 @@ class AVRInstrInfo : public AVRGenInstrInfo {
int FrameIndex, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
Register VReg) const override;
unsigned isLoadFromStackSlot(const MachineInstr &MI,
Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
unsigned isStoreToStackSlot(const MachineInstr &MI,
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

// Branch analysis.
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
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Expand Up @@ -330,7 +330,7 @@ Register CSKYInstrInfo::movImm(MachineBasicBlock &MBB,
return DstReg;
}

unsigned CSKYInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
Register CSKYInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
switch (MI.getOpcode()) {
default:
Expand Down Expand Up @@ -360,7 +360,7 @@ unsigned CSKYInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
return 0;
}

unsigned CSKYInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Register CSKYInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
switch (MI.getOpcode()) {
default:
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/CSKY/CSKYInstrInfo.h
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Expand Up @@ -35,9 +35,9 @@ class CSKYInstrInfo : public CSKYGenInstrInfo {
public:
explicit CSKYInstrInfo(CSKYSubtarget &STI);

unsigned isLoadFromStackSlot(const MachineInstr &MI,
Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
unsigned isStoreToStackSlot(const MachineInstr &MI,
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

void storeRegToStackSlot(MachineBasicBlock &MBB,
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
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Expand Up @@ -286,7 +286,7 @@ static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
Register HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
switch (MI.getOpcode()) {
default:
Expand Down Expand Up @@ -334,7 +334,7 @@ unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Register HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
switch (MI.getOpcode()) {
default:
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Hexagon/HexagonInstrInfo.h
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Expand Up @@ -54,15 +54,15 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
unsigned isLoadFromStackSlot(const MachineInstr &MI,
Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

/// If the specified machine instruction is a direct
/// store to a stack slot, return the virtual or physical register number of
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
unsigned isStoreToStackSlot(const MachineInstr &MI,
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

/// Check if the instruction or the bundle of instructions has
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
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Expand Up @@ -710,7 +710,7 @@ unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB,
return Count;
}

unsigned LanaiInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
Register LanaiInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
if (MI.getOpcode() == Lanai::LDW_RI)
if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
Expand All @@ -721,7 +721,7 @@ unsigned LanaiInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
return 0;
}

unsigned LanaiInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
Register LanaiInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
int &FrameIndex) const {
if (MI.getOpcode() == Lanai::LDW_RI) {
unsigned Reg;
Expand All @@ -739,7 +739,7 @@ unsigned LanaiInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
return 0;
}

unsigned LanaiInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Register LanaiInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
if (MI.getOpcode() == Lanai::SW_RI)
if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/Lanai/LanaiInstrInfo.h
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Expand Up @@ -38,13 +38,13 @@ class LanaiInstrInfo : public LanaiGenInstrInfo {
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
const MachineInstr &MIb) const override;

unsigned isLoadFromStackSlot(const MachineInstr &MI,
Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
int &FrameIndex) const override;

unsigned isStoreToStackSlot(const MachineInstr &MI,
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Mips/Mips16InstrInfo.cpp
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Expand Up @@ -51,7 +51,7 @@ const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
unsigned Mips16InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
Register Mips16InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
return 0;
}
Expand All @@ -61,7 +61,7 @@ unsigned Mips16InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
unsigned Mips16InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Register Mips16InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
return 0;
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Mips/Mips16InstrInfo.h
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Expand Up @@ -37,15 +37,15 @@ class Mips16InstrInfo : public MipsInstrInfo {
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
unsigned isLoadFromStackSlot(const MachineInstr &MI,
Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

/// isStoreToStackSlot - If the specified machine instruction is a direct
/// store to a stack slot, return the virtual or physical register number of
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
unsigned isStoreToStackSlot(const MachineInstr &MI,
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
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Expand Up @@ -42,7 +42,7 @@ const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
Register MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
unsigned Opc = MI.getOpcode();

Expand All @@ -64,7 +64,7 @@ unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Register MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
unsigned Opc = MI.getOpcode();

Expand Down
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