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@Koichi98 Koichi98 commented Aug 29, 2025

Description

This PR completes the DMA mapping layer by adding synchronization operations for bounce buffers and cache coherency, plus integration with pre-allocated DMA pools.

DMA Synchronization (sync method)

  • Bounce buffer synchronization: Automatically copies data between original buffers and bounce buffers at the right timing
    • PreWrite: Copies from original to bounce buffer before device writes
    • PostRead: Copies from bounce buffer to original after device reads
  • Cache coherency placeholders: Framework for cache invalidation/flush operations on non-coherent architectures (currently uses memory barriers only)
  • Architecture-specific handling: Prepared for RISC-V and AArch64 cache operations

Design Decisions

Deferred cache operations:
The current implementation uses memory barriers as a placeholder for full cache management. While sufficient for cache-coherent systems (like most x86_64), proper cache invalidation/flush operations are needed for non-coherent architectures. The TODO comments mark where architecture-specific cache operations should be added when non-coherent device support is required.

Related links

bus_dmamap_sync
https://github.com/openbsd/src/blob/95647c95e86787fd3d10394754ce3752dc75799c/sys/arch/amd64/amd64/bus_dma.c#L515

How was this PR tested?

Notes for reviewers

Signed-off-by: Koichi <[email protected]>
Base automatically changed from feat/dmamap to main September 12, 2025 01:53
@Koichi98 Koichi98 marked this pull request as ready for review September 23, 2025 02:09
@Koichi98 Koichi98 requested review from ytakano and veqcc September 24, 2025 01:49
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