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Merge branch 'main' into linty_test
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stnolting committed Oct 3, 2024
2 parents 172c0e7 + 750f141 commit eb71014
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Showing 6 changed files with 13 additions and 5 deletions.
2 changes: 1 addition & 1 deletion docs/datasheet/soc.adoc
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Expand Up @@ -196,7 +196,7 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
|=======================
| Name | Type | Default | Description
4+^| **General**
| `CLOCK_FREQUENCY` | natural | - | The clock frequency of the processor's `clk_i` input port in Hertz (Hz).
| `CLOCK_FREQUENCY` | natural | 0 | The clock frequency of the processor's `clk_i` input port in Hertz (Hz).
| `CLOCK_GATING_EN` | boolean | false | Enable clock gating when CPU is in sleep mode (see sections <<_sleep_mode>> and <<_processor_clocking>>).
| `INT_BOOTLOADER_EN` | boolean | false | Implement the processor-internal <<_bootloader_rom_bootrom>>, pre-initialized with the default <<_bootloader>> image.
| `HART_ID` | suv(31:0) | 0x00000000 | The hart thread ID of the CPU (passed to <<_mhartid>> CSR).
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2 changes: 1 addition & 1 deletion rtl/core/neorv32_package.vhd
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Expand Up @@ -668,7 +668,7 @@ package neorv32_package is
component neorv32_top
generic (
-- General --
CLOCK_FREQUENCY : natural;
CLOCK_FREQUENCY : natural := 0;
CLOCK_GATING_EN : boolean := false;
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000";
JEDEC_ID : std_ulogic_vector(10 downto 0) := "00000000000";
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6 changes: 5 additions & 1 deletion rtl/core/neorv32_top.vhd
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Expand Up @@ -22,7 +22,7 @@ use neorv32.neorv32_package.all;
entity neorv32_top is
generic (
-- General --
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
CLOCK_GATING_EN : boolean := false; -- enable clock gating when in sleep mode
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID
JEDEC_ID : std_ulogic_vector(10 downto 0) := "00000000000"; -- JEDEC ID: continuation codes + vendor ID
Expand Down Expand Up @@ -374,6 +374,10 @@ begin
assert not (io_sysinfo_en_c = false) report
"[NEORV32] SYSINFO module disabled - some parts of the NEORV32 software framework will no longer work!" severity warning;

-- Clock speed not defined --
assert not (CLOCK_FREQUENCY = 0) report
"[NEORV32] CLOCK_FREQUENCY must be configured according to the frequency of clk_i port!" severity warning;

end generate; -- /sanity_checks


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2 changes: 1 addition & 1 deletion sim/simple/ghdl.run.sh
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Expand Up @@ -4,7 +4,7 @@ set -e

cd $(dirname "$0")

echo "Tip: Compile application with USER_FLAGS+=-DUART[0/1]_SIM_MODE to auto-enable UART[0/1]'s simulation mode (redirect UART output to simulator console)."
echo "[TIP] Compile application with USER_FLAGS+=-DUART[0/1]_SIM_MODE to enable UART[0/1]'s simulation mode (redirect UART output to simulator console)."

# Prepare simulation output files for UART0 and UART 1
# - Testbench receiver log file (neorv32.testbench_uart?.out)
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2 changes: 1 addition & 1 deletion sw/common/common.mk
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Expand Up @@ -153,7 +153,7 @@ target bootloader | bl_image: CC_OPTS += -Wl,--defsym=MAKE_BOOTLOADER=1 -DMAKE_B
# -----------------------------------------------------------------------------
# Compile image generator
$(IMAGE_GEN): $(NEORV32_EXG_PATH)/image_gen.c
@echo Compiling $(IMAGE_GEN)
@echo Compiling image generator...
@$(CC_HOST) $< -o $(IMAGE_GEN)

# -----------------------------------------------------------------------------
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4 changes: 4 additions & 0 deletions sw/image_gen/image_gen.c
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Expand Up @@ -83,6 +83,10 @@ int main(int argc, char *argv[]) {
unsigned int input_words = input_size / 4;
rewind(input);

if ((input_size % 4) != 0) {
printf("WARNING - image size is not a multiple of 4 bytes.\n");
}

// input file empty?
if(input_size == 0) {
printf("Input file is empty!");
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