Merge branch 'main' into linty_test

stnolting · Oct 5, 2024 · b0ec0b0 · b0ec0b0
2 parents f578329 + a8c776e
commit b0ec0b0
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diff --git a/.github/workflows/Documentation.yml b/.github/workflows/Documentation.yml
@@ -4,9 +4,11 @@ on:
   push:
     paths:
     - 'docs/**'
+    - '.github/workflows/**'
   pull_request:
     paths:
     - 'docs/**'
+    - '.github/workflows/**'
   workflow_dispatch:
 
 jobs:

diff --git a/.github/workflows/Processor.yml b/.github/workflows/Processor.yml
@@ -2,15 +2,17 @@ name: Processor
 
 on:
   push:
-    branches:
+    paths:
     - 'rtl/**'
     - 'sw/**'
     - 'sim/**'
+    - '.github/workflows/**'
   pull_request:
     paths:
     - 'rtl/**'
     - 'sw/**'
     - 'sim/**'
+    - '.github/workflows/**'
   workflow_dispatch:
 
 jobs:

diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc
@@ -69,7 +69,13 @@ bits/channels are hardwired to zero.
 
 .Tri-State Interfaces
 [NOTE]
-Some interfaces (like the TWI and the 1-Wire bus) require tri-state drivers in the designs top module.
+Some interfaces (like the TWI and the 1-Wire bus) require explicit tri-state drivers in the final top module.
+
+.Input/Output Registers
+[NOTE] 
+By default all output signals are driven by register and all input signals are synchronized into the processor's
+clock domain also using registers. However, for ASIC implementations it is recommended to add another register state
+to all inputs and output so the synthesis tool can insert an explicit IO (boundary) scan chain.
 
 .NEORV32 Processor Signal List
 [cols="<3,^1,^1,^1,<8"]
@@ -154,9 +160,9 @@ Some interfaces (like the TWI and the 1-Wire bus) require tri-state drivers in t
 5+^| **<<_external_interrupt_controller_xirq>>**
 | `xirq_i`         | 32 |  in | `'L'` | external interrupt requests
 5+^| **RISC-V Machine-Mode <<_processor_interrupts>>**
-| `mtime_irq_i`    |  1 |  in | `'L'` | machine timer interrupt (RISC-V), high-level-active
-| `msw_irq_i`      |  1 |  in | `'L'` | machine software interrupt (RISC-V), high-level-active
-| `mext_irq_i`     |  1 |  in | `'L'` | machine external interrupt (RISC-V), high-level-active
+| `mtime_irq_i`    |  1 |  in | `'L'` | machine timer interrupt (RISC-V), high-level-active; for chip-internal usage only
+| `msw_irq_i`      |  1 |  in | `'L'` | machine software interrupt (RISC-V), high-level-active; for chip-internal usage only
+| `mext_irq_i`     |  1 |  in | `'L'` | machine external interrupt (RISC-V), high-level-active; for chip-internal usage only
 |=======================
 
 

diff --git a/docs/datasheet/soc_cfs.adoc b/docs/datasheet/soc_cfs.adoc
@@ -84,6 +84,8 @@ generic (default = 32-bit). The size of the output signal conduit `cfs_out_o` is
 `IO_CFS_OUT_SIZE` configuration generic (default = 32-bit). If the custom function subsystem is not implemented
 (`IO_CFS_EN` = false) the `cfs_out_o` signal is tied to all-zero.
 
+If the CFU output signals are to be used outside the chip, it is recommended to register these signals.
+
 
 **Register Map**
 

diff --git a/docs/figures/neorv32_bus.png b/docs/figures/neorv32_bus.png
diff --git a/docs/figures/neorv32_processor.png b/docs/figures/neorv32_processor.png
diff --git a/rtl/core/neorv32_cfs.vhd b/rtl/core/neorv32_cfs.vhd
@@ -61,6 +61,8 @@ begin
   -- -------------------------------------------------------------------------------------------
   -- By default, the CFS provides two IO signals (cfs_in_i and cfs_out_o) that are available at the processor's top entity.
   -- These are intended as "conduits" to propagate custom signals from this module and the processor top entity.
+  --
+  -- If the CFU output signals are to be used outside the chip, it is recommended to register these signals.
 
   cfs_out_o <= (others => '0'); -- not used for this minimal example
 

diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd
@@ -235,7 +235,7 @@ entity neorv32_top is
     -- External platform interrupts (available if XIRQ_NUM_CH > 0) --
     xirq_i         : in  std_ulogic_vector(31 downto 0) := (others => 'L'); -- IRQ channels
 
-    -- CPU interrupts --
+    -- CPU interrupts (for chip-internal usage only) --
     mtime_irq_i    : in  std_ulogic := 'L';                                 -- machine timer interrupt, available if IO_MTIME_EN = false
     msw_irq_i      : in  std_ulogic := 'L';                                 -- machine software interrupt
     mext_irq_i     : in  std_ulogic := 'L'                                  -- machine external interrupt