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Update stm32l1 crate to v0.12.1 #11

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3660845
Update device crate to v0.7.1
jyrama Oct 4, 2020
1964ebf
Update device crate to v0.8.0
jyrama Oct 4, 2020
e544df1
Update device crate to v0.12.1
jyrama Oct 4, 2020
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6 changes: 3 additions & 3 deletions Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -21,9 +21,9 @@ repository = "https://github.com/stm32-rs/stm32l1xx-hal"
version = "0.1.0"

[dependencies]
cortex-m = "0.5.8"
cortex-m = "0.6.3"
nb = "0.1.1"
stm32l1 = "0.5.0"
stm32l1 = "0.12.1"

[dependencies.bare-metal]
features = ["const-fn"]
Expand All @@ -35,7 +35,7 @@ version = "0.2.2"

[dependencies.embedded-hal]
features = ["unproven"]
version = "0.2.3"
version = "0.2.4"

[dependencies.void]
default-features = false
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6 changes: 4 additions & 2 deletions examples/button_irq.rs
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Expand Up @@ -23,9 +23,11 @@ static INT: Mutex<RefCell<Option<EXTI>>> = Mutex::new(RefCell::new(None));
#[entry]
fn main() -> ! {
let dp = stm32::Peripherals::take().unwrap();
let mut cp = cortex_m::Peripherals::take().unwrap();

cp.NVIC.enable(Interrupt::EXTI0);
unsafe {
cortex_m::peripheral::NVIC::unmask(Interrupt::EXTI0);
}

dp.EXTI.listen(0, TriggerEdge::Falling);

cortex_m::interrupt::free(move |cs| {
Expand Down
5 changes: 3 additions & 2 deletions examples/timer.rs
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Expand Up @@ -23,13 +23,14 @@ static TIMER: Mutex<RefCell<Option<Timer<stm32::TIM2>>>> = Mutex::new(RefCell::n
#[entry]
fn main() -> ! {
let dp = stm32::Peripherals::take().unwrap();
let mut cp = cortex_m::Peripherals::take().unwrap();
let mut rcc = dp.RCC.freeze(Config::hsi());

let mut timer = dp.TIM2.timer(1.hz(), &mut rcc);
timer.listen();

cp.NVIC.enable(Interrupt::TIM2);
unsafe {
cortex_m::peripheral::NVIC::unmask(Interrupt::TIM2);
}

cortex_m::interrupt::free(move |cs| {
*TIMER.borrow(cs).borrow_mut() = Some(timer);
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26 changes: 13 additions & 13 deletions src/pwm.rs
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Expand Up @@ -54,22 +54,22 @@ macro_rules! channels {
fn enable(&mut self) {
unsafe {
let tim = &*$TIMX::ptr();
tim.ccmr1_output
tim.ccmr1_output()
.modify(|_, w| w.oc1pe().set_bit().oc1m().bits(6));
tim.ccer.modify(|_, w| w.cc1e().set_bit());
}
}

fn get_duty(&self) -> u16 {
unsafe { (*$TIMX::ptr()).ccr1.read().ccr1().bits() }
unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() }
}

fn get_max_duty(&self) -> u16 {
unsafe { (*$TIMX::ptr()).arr.read().arr().bits() }
}

fn set_duty(&mut self, duty: u16) {
unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr1().bits(duty)) }
unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty)) }
}
}
};
Expand Down Expand Up @@ -137,22 +137,22 @@ macro_rules! channels {
fn enable(&mut self) {
unsafe {
let tim = &*$TIMX::ptr();
tim.ccmr1_output
tim.ccmr1_output()
.modify(|_, w| w.oc2pe().set_bit().oc2m().bits(6));
tim.ccer.modify(|_, w| w.cc2e().set_bit());
}
}

fn get_duty(&self) -> u16 {
unsafe { (*$TIMX::ptr()).ccr2.read().ccr2().bits() }
unsafe { (*$TIMX::ptr()).ccr2.read().ccr().bits() }
}

fn get_max_duty(&self) -> u16 {
unsafe { (*$TIMX::ptr()).arr.read().arr().bits() }
}

fn set_duty(&mut self, duty: u16) {
unsafe { (*$TIMX::ptr()).ccr2.write(|w| w.ccr2().bits(duty)) }
unsafe { (*$TIMX::ptr()).ccr2.write(|w| w.ccr().bits(duty)) }
}
}

Expand All @@ -168,22 +168,22 @@ macro_rules! channels {
fn enable(&mut self) {
unsafe {
let tim = &*$TIMX::ptr();
tim.ccmr2_output
tim.ccmr2_output()
.modify(|_, w| w.oc3pe().set_bit().oc3m().bits(6));
tim.ccer.modify(|_, w| w.cc3e().set_bit());
}
}

fn get_duty(&self) -> u16 {
unsafe { (*$TIMX::ptr()).ccr3.read().ccr3().bits() }
unsafe { (*$TIMX::ptr()).ccr3.read().ccr().bits() }
}

fn get_max_duty(&self) -> u16 {
unsafe { (*$TIMX::ptr()).arr.read().arr().bits() }
}

fn set_duty(&mut self, duty: u16) {
unsafe { (*$TIMX::ptr()).ccr3.write(|w| w.ccr3().bits(duty)) }
unsafe { (*$TIMX::ptr()).ccr3.write(|w| w.ccr().bits(duty)) }
}
}

Expand All @@ -199,22 +199,22 @@ macro_rules! channels {
fn enable(&mut self) {
unsafe {
let tim = &*$TIMX::ptr();
tim.ccmr2_output
tim.ccmr2_output()
.modify(|_, w| w.oc4pe().set_bit().oc4m().bits(6));
tim.ccer.modify(|_, w| w.cc4e().set_bit());
}
}

fn get_duty(&self) -> u16 {
unsafe { (*$TIMX::ptr()).ccr4.read().ccr4().bits() }
unsafe { (*$TIMX::ptr()).ccr4.read().ccr().bits() }
}

fn get_max_duty(&self) -> u16 {
unsafe { (*$TIMX::ptr()).arr.read().arr().bits() }
}

fn set_duty(&mut self, duty: u16) {
unsafe { (*$TIMX::ptr()).ccr4.write(|w| w.ccr4().bits(duty)) }
unsafe { (*$TIMX::ptr()).ccr4.write(|w| w.ccr().bits(duty)) }
}
}
};
Expand Down Expand Up @@ -257,7 +257,7 @@ macro_rules! timers {
let ticks = clk / freq;
let psc = u16((ticks - 1) / (1 << 16)).unwrap();
let arr = u16(ticks / u32(psc + 1)).unwrap();
tim.psc.write(|w| unsafe { w.psc().bits(psc) });
tim.psc.write(|w| w.psc().bits(psc) );
#[allow(unused_unsafe)]
tim.arr.write(|w| unsafe { w.arr().bits(arr) });
tim.cr1.write(|w| w.cen().set_bit());
Expand Down
4 changes: 2 additions & 2 deletions src/qei.rs
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Expand Up @@ -63,7 +63,7 @@ macro_rules! hal {
rcc.rb.apb1rstr.modify(|_, w| w.$timXrst().clear_bit());

// Configure TxC1 and TxC2 as captures
tim.ccmr1_output.write(|w| unsafe {
tim.ccmr1_output().write(|w| unsafe {
w.cc1s().bits(0b01).cc2s().set_bit()
});

Expand All @@ -84,7 +84,7 @@ macro_rules! hal {
});

// Encoder mode, count up/down on both TI1FP1 and TI2FP2
tim.smcr.write(|w| unsafe { w.sms().bits(0b011) });
tim.smcr.write(|w| w.sms().bits(0b011) );

tim.arr.write(|w| w.arr().bits(u16::MAX));
tim.cr1.write(|w| w.cen().enabled());
Expand Down
2 changes: 1 addition & 1 deletion src/timer.rs
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Expand Up @@ -151,7 +151,7 @@ macro_rules! timers {
let ticks = self.clocks.$timclk().0 / freq;
let psc = u16((ticks - 1) / (1 << 16)).unwrap();

self.tim.psc.write(|w| unsafe { w.psc().bits(psc) });
self.tim.psc.write(|w| w.psc().bits(psc) );
self.tim.arr.write(|w| unsafe { w.bits(ticks / u32(psc + 1)) });

self.tim.cr1.modify(|_, w| w.urs().set_bit());
Expand Down