Arnicomp Support Package is a collection of software tools built to support Arnicomp, a custom-designed 8-bit breadboard computer.
Rather than focusing on a single component, this repository brings together all auxiliary tooling required to assemble, simulate, debug, and work with the Arnicomp architecture.
- Digital.exe simulation models
- Logic-level simulation files used to validate the Arnicomp hardware design
- Allows inspection of signal flow, control logic, and timing behavior
- Fully functional Arnicomp assembler
- Converts Arnicomp assembly language into executable machine code
- Features:
- Label resolution
- Constant definitions
- Complete support for the latest ISA
- This directory contains the current and stable assembler implementation
- Current (Newest ISA :) )
- Old ISA
- Arnicomp CPU emulator
- Emulates the processor cycle-by-cycle with hardware-accurate behavior
- Executes assembled machine code exactly as the physical CPU would
- Primarily used for:
- Debugging programs
- Verifying instruction semantics
- Testing assembler output without physical hardware
- Graphical user interface for the emulator
- Designed to work directly with
/emulator - Enables:
- Loading and editing assembly files
- Step-by-step execution
- Breakpoints
- Register and flag inspection
- The UI was largely AI-assisted, as frontend development is not the primary focus of the project
- Incomplete compiler prototype
- Not finished in this repository
- Compiler development has continued in a separate repository, restarted from scratch
- This directory remains for historical reference only
- Visual Studio Code extension
- Provides syntax highlighting for the Arnicomp assembly language
- Makes writing and reading assembly code significantly easier
- The project went through two major instruction set and architecture revisions during development
- As a result, some directory structure and legacy files may appear inconsistent
- Older designs were intentionally preserved to:
- Track architectural evolution
- Avoid breaking working tooling
- Serve as reference during ISA redesigns
-
Except for the emulator UI, AI-generated code usage is minimal
-
Core components such as:
- Assembler
- Emulator
- ISA design
were written and verified manually
-
AI assistance was mainly used for:
- UI layout generation
- Boilerplate frontend code
- Minor refactors and documentation drafts
During development, the original opcode/argcode-based instruction format was replaced with the current final 8-bit ISA used by the assembler and Verilog implementation.
Key characteristics of the current ISA include:
LDL/LDHsplit byte construction forRAandRD- unified
MOVencoding (10 ddd sss) - source-side
ZERO,LRL, andLRHbus options - arithmetic family using
RDas the left operand:ADD,ADDI,ADCSUB,SUBI,SBCCMP
- logical operations:
XOR,AND,NOT
- stack operations:
PUSH,POP
- MAR update operations:
INC #1/#2DEC #1/#2
- jump family based on
Z/N/C/Vflags:JEQ,JNE,JCS,JCC,JMI,JVS,JLT,JMPJGTas the dedicated extra opcodeJALfor link-and-jump throughPRH:PRL
LRL/LRHreplacing the older directPCreadback model
Assembler-side productivity features now include pseudoinstructions such as:
LDICALLJMPARETPUSHIPUSHSTR
The assembler README documents the current split between:
- real ISA instructions
- assembler pseudoinstructions/macros
- aliases
Legacy documentation remains in arnicomp_details.txt for historical context.
| Component | Status |
|---|---|
| Assembler | ✅ Complete |
| Emulator | ✅ Complete |
| Emulator UI | ✅ Complete |
| VS Code Extension | ✅ Complete |
| Compiler | 🚧 Continued in separate repo |
This project is primarily intended for educational, experimental, and personal hardware development purposes.
Feedback on:
- ISA design
- Emulator accuracy
- Tooling structure
is always welcome.
Arnicomp is a long-term exploration of CPU design, tooling, and low-level software — not just a single assembler.