GitHub - skristiansson/i2s: i2s core, with support for both transmit and receive

Name	Name	Last commit message	Last commit date
Latest commit skristiansson add a wishbone configuration interface Sep 28, 2014 a0e2e50 · Sep 28, 2014 History 13 Commits
bench	bench	add prescaler to tx lrclk generation	Sep 28, 2014
rtl/verilog	rtl/verilog	add a wishbone configuration interface	Sep 28, 2014
.gitignore	.gitignore	Initial commit	Oct 16, 2013
.travis.yml	.travis.yml	travis: update travis script from orpsoc to fusesoc	Sep 28, 2014
i2s.core	i2s.core	Initial commit	Oct 16, 2013