Updating lambdalib for new SC design API

.flake8

@@ -1,4 +1,6 @@
 [flake8]
 max-line-length = 100
 extend-exclude = build,.venv
-extend-ignore = 
+extend-ignore =
+per-file-ignores =
+    lambdalib/__init__.py:F401

.gitignore

@@ -1,12 +1,19 @@
-
 #Editor files
 *~
-*~
+
+.vscod
+
+#Env
+venv/
+.venv
+
+
+# Sim
 *.log
-tmp*
-a.out
 *.vcd
-.venv/
+a.out
+*.vvp
+*.f
 
 # Byte-compiled / optimized / DLL files
 __pycache__/

README.md

@@ -1,23 +1,66 @@
 # Lambdalib Introduction
 
-Lambdalib is a modular hardware abstraction library which decouples design from the underlying manufacturing target. Lambdalib defines a set of generic functions that get resolved during the target technology mapping stage.
+Lambdalib is a modular hardware abstraction library which decouples design from the manufacturing target. The project was inspired by the `Lambda` concept invented during the [1978 VLSI revolution by Mead and Conway](https://en.wikipedia.org/wiki/Mead%E2%80%93Conway_VLSI_chip_design_revolution).
 
-Lambdalib includes the following hardware categories:
+The original single value Lambda approach no longer applies to modern CMOS manufacturing, so Lambdalib has raised the abstraction level to the cell/block level to enable automated porting between compilation targets.
+
+Lambdalib abstracts away technology specific design modules that cannot be cleanly expressed in technology agnostic RTL Verilog code (eg. synchronizers, analog circuits, io cells, etc.)
+
+The table below summarizes the categories of cells available.
 
 | Category                            | Description                           |
 |-------------------------------------|---------------------------------------|
 |[stdlib](lambdalib/stdlib/rtl)       | Standard cells (inv, nand, ff, ...)
-|[auxlib](lambdalib/auxlib/rtl)       | Aux cells can consist of multiple standard cells or physical only cells
+|[auxlib](lambdalib/auxlib/rtl)       | Special cells (antenna, decap, clkmux,...)
 |[ramlib](lambdalib/ramlib/rtl)       | Memory (single port, dual port, fifo, ...)
 |[iolib](lambdalib/iolib)             | IO cells (bidir, vdd, clamp,...)
 |[padring](lambdalib/padring)         | Padring generator
-|[vectorlib](lambdalib/vectorlib/rtl) | Vectorized library (mux, isolation)
+|[veclib](lambdalib/veclib/rtl)       | Vectorized datapath cells (mux, buf,..)
 |[fpgalib](lambdalib/fpgalib/rtl)     | FPGA cells (lut4, ble, clb)
 
 The [Lambdapdk](https://github.com/siliconcompiler/lambdapdk) repository demonstrates implementation of the Lambdalib interfaces across a number of open source process technologies.
 
 Lambdalib has been successfully used in multiple tapeouts using [SiliconCompiler](https://github.com/siliconcompiler/siliconcompiler).
 
+# Installation
+
+```bash
+git clone https://github.com/zeroasiccorp/lambdalib
+cd lambdalib
+pip install --upgrade pip
+pip install -e .
+```
+
+# Examples
+
+## Instantiating a Lambdalib module
+
+This example shows how to instantiate the Padring module in a top level chip design.
+We could have chosen any module to instantiate (inverter, flip flop, dual port ram...).
+
+
+```python
+```
+
+To convert the design into a gate level netlist using yosys, just run python script
+in the examples folder. A file `chip.vg` will be written to disk in the run directory.
+
+```bash
+$ python examples/padring/make.py
+```
+
+## Using SiliconCompiler to target a technology
+
+```python
+```
+
+
+# Project Methodology
+
+- One verilog module per RTL file
+- One Python module per reusable module
+- Class names are RTL module names with "la_" removed and capitalized
+
 # License
 
 [MIT](LICENSE)

examples/chip/chip.py

@@ -0,0 +1,34 @@
+import lambdalib as ll
+from siliconcompiler import DesignSchema
+
+class Chip(DesignSchema):
+    def __init__(self):
+
+        name = 'chip'
+        super().__init__(name)
+
+        fileset = 'rtl'
+        dataroot = f'{name}'
+        topmodule = name
+
+        sources = [f'rtl/{name}.v']
+
+        self.set_dataroot(dataroot, __file__)
+        self.set_topmodule(topmodule, fileset)
+
+        for item in sources:
+            self.add_file(item, fileset, dataroot=dataroot)
+
+        self.add_idir('rtl', fileset, dataroot=dataroot)
+
+        # dependencies
+        for dep in [ll.padring.Padring]:
+            self.add_depfileset(dep(), depfileset='rtl', fileset='rtl')
+
+if __name__ == "__main__":
+    d = Chip()
+    d.write_fileset(f"{d.name()}.f", fileset="rtl")
+    cmd = ['yosys', '-f', script]
+    return subprocess.run(cmd,
+                          stderr=subprocess.STDOUT,
+                          check=True)

examples/chip/rtl/chip.v

@@ -0,0 +1,115 @@
+module chip #(parameter NO_NPINS = 16,
+              parameter EA_NPINS = 16,
+              parameter WE_NPINS = 16,
+              parameter SO_NPINS = 16)
+   (
+    input                VSS,
+    input                VDD,
+    input                NVCC,
+    input                EVCC,
+    input                WVCC,
+    input                SVCC,
+    inout [NO_NPINS-1:0] NIO,
+    inout [EA_NPINS-1:0] EIO,
+    inout [WE_NPINS-1:0] WIO,
+    inout [SO_NPINS-1:0] SIO
+    );
+
+`include "chip_iomap.vh"
+
+   wire [NO_NSECTIONS*RINGW-1:0] no_ioring;
+   wire [EA_NSECTIONS*RINGW-1:0] ea_ioring;
+   wire [WE_NSECTIONS*RINGW-1:0] we_ioring;
+   wire [SO_NSECTIONS*RINGW-1:0] so_ioring;
+
+   wire [NO_NPINS-1:0] no_rxd;
+   wire [EA_NPINS-1:0] ea_rxd;
+   wire [WE_NPINS-1:0] we_rxd;
+   wire [SO_NPINS-1:0] so_rxd;
+
+   la_padring #(// padring ctrl widths
+                .RINGW(RINGW),
+                .CFGW(CFGW),
+                //north
+                .NO_NPINS(NO_NPINS),
+                .NO_NCELLS(NO_NCELLS),
+                .NO_NSECTIONS(NO_NSECTIONS),
+                .NO_CELLMAP(NO_CELLMAP),
+                //east
+                .EA_NPINS(EA_NPINS),
+                .EA_NCELLS(EA_NCELLS),
+                .EA_NSECTIONS(EA_NSECTIONS),
+                .EA_CELLMAP(EA_CELLMAP),
+                //south
+                .SO_NPINS(SO_NPINS),
+                .SO_NCELLS(SO_NCELLS),
+                .SO_NSECTIONS(SO_NSECTIONS),
+                .SO_CELLMAP(SO_CELLMAP),
+                //west
+                .WE_NPINS(WE_NPINS),
+                .WE_NCELLS(WE_NCELLS),
+                .WE_NSECTIONS(WE_NSECTIONS),
+                .WE_CELLMAP(WE_CELLMAP))
+   la_padring(// Outputs
+              .no_zp            (no_rxd[NO_NPINS-1:0]),
+              .no_zn            (),
+              .ea_zp            (ea_rxd[EA_NPINS-1:0]),
+              .ea_zn            (),
+              .so_zp            (so_rxd[SO_NPINS-1:0]),
+              .so_zn            (),
+              .we_zp            (we_rxd[WE_NPINS-1:0]),
+              .we_zn            (),
+              // Inouts
+              .vss              (VSS),
+              .no_pad           (NIO),
+              .no_aio           (),
+              .no_vdd           (VDD),
+              .no_vddio         (NVCC),
+              .no_vssio         (VSS),
+              .no_ioring        (no_ioring[NO_NSECTIONS*RINGW-1:0]),
+              .ea_pad           (EIO),
+              .ea_aio           (),
+              .ea_vdd           (VDD),
+              .ea_vddio         (EVCC),
+              .ea_vssio         (VSS),
+              .ea_ioring        (ea_ioring[EA_NSECTIONS*RINGW-1:0]),
+              .so_pad           (SIO),
+              .so_aio           (),
+              .so_vdd           (VDD),
+              .so_vddio         (SVCC),
+              .so_vssio         (VSS),
+              .so_ioring        (so_ioring[SO_NSECTIONS*RINGW-1:0]),
+              .we_pad           (WIO),
+              .we_aio           (),
+              .we_vdd           (VDD),
+              .we_vddio         (WVCC),
+              .we_vssio         (VSS),
+              .we_ioring        (we_ioring[WE_NSECTIONS*RINGW-1:0]),
+              // Inputs
+              .no_a             ({NO_NPINS{1'b0}}),
+              .no_ie            ({NO_NPINS{1'b1}}),
+              .no_oe            ({NO_NPINS{1'b0}}),
+              .no_pe            ({NO_NPINS{1'b0}}),
+              .no_ps            ({NO_NPINS{1'b0}}),
+              .no_cfg           ({(NO_NPINS*CFGW){1'b0}}),
+              .ea_a             ({EA_NPINS{1'b0}}),
+              .ea_ie            ({EA_NPINS{1'b1}}),
+              .ea_oe            ({EA_NPINS{1'b0}}),
+              .ea_pe            ({EA_NPINS{1'b0}}),
+              .ea_ps            ({EA_NPINS{1'b0}}),
+              .ea_cfg           ({(EA_NPINS*CFGW){1'b0}}),
+              .we_a             ({WE_NPINS{1'b0}}),
+              .we_ie            ({WE_NPINS{1'b1}}),
+              .we_oe            ({WE_NPINS{1'b0}}),
+              .we_pe            ({WE_NPINS{1'b0}}),
+              .we_ps            ({WE_NPINS{1'b0}}),
+              .we_cfg           ({(WE_NPINS*CFGW){1'b0}}),
+              .so_a             ({SO_NPINS{1'b0}}),
+              .so_ie            ({SO_NPINS{1'b1}}),
+              .so_oe            ({SO_NPINS{1'b0}}),
+              .so_pe            ({SO_NPINS{1'b0}}),
+              .so_ps            ({SO_NPINS{1'b0}}),
+              .so_cfg           ({(SO_NPINS*CFGW){1'b0}})
+              );
+
+endmodule

examples/chip/rtl/chip_iomap.vh

@@ -0,0 +1,108 @@
+//########################################################################
+// Common Padring Definitions
+//########################################################################
+
+`include "la_padring.vh"
+
+//########################################################################
+// Total number of IO cells in one padring side (including power)
+//########################################################################
+
+// 16 bidirs
+// 12 power ground
+// 2 cut cells
+// 1 poc
+
+localparam NCELLS = 31;
+
+//########################################################################
+// Power sections per side
+//########################################################################
+
+localparam NSECTIONS = 1;
+
+//########################################################################
+// Tech specific iolib parameters
+//########################################################################
+
+// total width of config bus (drive strength, schmitt, ...)
+localparam CFGW = 6;
+
+// width of bus that goes around ioring
+localparam RINGW = 6;
+
+//########################################################################
+// CELLMAP[NCELLS*40-1:0] = {PROP, SECTION, CELL, CPIN#, PIN#}
+//########################################################################
+
+/* The CELLMAP vector specifies the type, order,  power rail, and pin
+ * connection for each cell placed in a side of the io padring.
+ *
+ * CELLMAP is used by la_padside which iterates from 0 to NCELLS-1 to
+ * instantiate padring cells. The index for that for loop is used
+ * to find the power section, pin number, and cell type in the
+ * static definition below. The indices of the cells are specified from
+ * left to right or top to bottom. The CELLMAP[0] is the first cell
+ * placed.
+ *
+ * All enumerationsa arer defined in the la_iopadring.vh
+ *
+ * [7:0]   PIN#            = pin# (order 0-255)
+ * [15:8]  COMPLEMENT PIN# = pin# (order 0-255)
+ * [23:16] CELL            = cell type from lambdalib (0-255)
+ * [31:24] SECTION         = power rail selector (when NSECTIONS>1)
+ * [39:32] PROP            = cell property (optional)
+ *
+ */
+
+localparam [NCELLS*40-1:0] CELLMAP =
+                           {{NULL, NULL,  LA_CUT,    NULL, NULL},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN15},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN14},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN13},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN12},
+                            {NULL, NULL,  LA_VSS,    NULL, NULL},
+                            {NULL, NULL,  LA_VDD,    NULL, NULL},
+                            {NULL, NULL,  LA_VDDIO,  NULL, NULL},
+                            {NULL, NULL,  LA_VSSIO,  NULL, NULL},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN11},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN10},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN9},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN8},
+                            {NULL, NULL,  LA_VSS,    NULL, NULL},
+                            {NULL, NULL,  LA_VDD,    NULL, NULL},
+                            {NULL, NULL,  LA_POC,    NULL, NULL},
+                            {NULL, NULL,  LA_VDDIO,  NULL, NULL},
+                            {NULL, NULL,  LA_VSSIO,  NULL, NULL},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN7},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN6},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN5},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN4},
+                            {NULL, NULL,  LA_VSS,    NULL, NULL},
+                            {NULL, NULL,  LA_VDD,    NULL, NULL},
+                            {NULL, NULL,  LA_VDDIO,  NULL, NULL},
+                            {NULL, NULL,  LA_VSSIO,  NULL, NULL},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN3},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN2},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN1},
+                            {NULL, NULL,  LA_BIDIR,  NULL, PIN0},
+                            {NULL, NULL,  LA_CUT,    NULL, NULL}};
+
+//########################################################################
+// Symmetrical padring for simplicity (not a restriction)
+//########################################################################
+
+localparam NO_NCELLS = NCELLS;
+localparam EA_NCELLS = NCELLS;
+localparam WE_NCELLS = NCELLS;
+localparam SO_NCELLS = NCELLS;
+
+localparam NO_NSECTIONS = NSECTIONS;
+localparam EA_NSECTIONS = NSECTIONS;
+localparam WE_NSECTIONS = NSECTIONS;
+localparam SO_NSECTIONS = NSECTIONS;
+
+localparam NO_CELLMAP = CELLMAP;
+localparam EA_CELLMAP = CELLMAP;
+localparam WE_CELLMAP = CELLMAP;
+localparam SO_CELLMAP = CELLMAP;

examples/sram/rtl/sram.v

@@ -0,0 +1,5 @@
+module sram();
+
+   // TODO: put in la_spram
+
+endmodule