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uart_packet: decoder for logging and analysis of uart packets of variable length #89

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@sespivak sespivak commented Jul 25, 2022

Decoder uart_packet stacks with uart decoder and allows to analyze data packets. Packet delimiter is idle time or maximum packet length. Output formats are same as in uart decoder: hex, dec, oct, bin and ascii.
Screenshot from 2022-07-26 12-11-17

'print_sec=yes' option can be used to log packets in real time:

sigrok-cli -d fx2lafw -c samplerate=1M --continuous \
           -P uart:rx=D4:tx=D5:baudrate=57600,uart_packet:print_sec=yes \
           -A uart_packet
uart_packet-1:    0.103 RX: AD 0C 80 00 80 80 80 80 80 00 00 00 00 00 00 A1
uart_packet-1:    0.301 TX: DA 03 00 00 B8 04 65
uart_packet-1:    0.303 RX: AD 04 80 00 00 00 00 29
uart_packet-1:    0.501 TX: DA 03 00 02 01 0C D6
uart_packet-1:    0.503 RX: AD 0C 80 00 80 80 80 80 80 00 00 00 00 00 00 A1
uart_packet-1:    0.702 TX: DA 03 00 00 B8 04 65
uart_packet-1:    0.703 RX: AD 04 80 00 00 00 00 29
uart_packet-1:    0.902 TX: DA 03 00 02 01 0C D6
uart_packet-1:    0.903 RX: AD 0C 80 00 80 80 80 80 80 00 00 00 00 00 00 A1
uart_packet-1:    1.112 TX: DA 03 00 00 B8 04 65
uart_packet-1:    1.113 RX: AD 04 80 00 00 00 00 29
uart_packet-1:    1.312 TX: DA 03 00 02 01 0C D6
uart_packet-1:    1.313 RX: AD 0C 80 00 80 80 80 80 80 00 00 00 00 00 00 A1

And one more example with input file:

sigrok-cli -i ~/sigrok/input.sr \
           -P uart,uart_packet:print_sec=yes:format=ascii \
           -A uart_packet
uart_packet-1:    5.882 TX err: \x00
uart_packet-1:    7.166 RX: \x00
uart_packet-1:   33.514 TX: AT\r
uart_packet-1:   33.515 RX: AT\r
uart_packet-1:   33.516 RX: \r\nOK\r\n
uart_packet-1:   41.114 TX: AT\r
uart_packet-1:   41.116 RX: AT\r
uart_packet-1:   41.116 RX: \r\nOK\r\n
uart_packet-1:   41.216 TX: ATI0\r
uart_packet-1:   41.218 RX: ATI0\r
uart_packet-1:   41.218 RX: \r\nSIM800 R14.18\r\n\r\nOK\r\n
uart_packet-1:   41.320 TX: AT+CGSN\r
uart_packet-1:   41.322 RX: AT+CGSN\r
uart_packet-1:   41.323 RX: \r\n868328057543908\r\n\r\nOK\r\n
uart_packet-1:   41.423 TX: AT+CGMR\r
uart_packet-1:   41.424 RX: AT+CGMR\r
uart_packet-1:   41.425 RX: \r\nRevision:1418B08SIM800C24_BT\r\n\r\nOK\r\n
uart_packet-1:   41.526 TX: AT+CLTS?\r
uart_packet-1:   41.528 RX: AT+CLTS?\r\r\n+CLTS: 0\r\n\r\nOK\r\n
uart_packet-1:   41.629 TX: AT+CCLK?\r
uart_packet-1:   41.631 RX: AT+CCLK?\r
uart_packet-1:   41.632 RX: \r\n+CCLK: "22/07/23,11:54:02+00"\r\n\r\nOK\r\n
uart_packet-1:   41.815 TX: AT+CSDT?\r
uart_packet-1:   41.816 RX: AT+CSDT?\r
uart_packet-1:   41.817 RX: \r\n+CSDT: 0\r\n\r\nOK\r\n
uart_packet-1:   41.919 TX: AT+CSMINS?\r
uart_packet-1:   41.921 RX: AT+CSMINS?\r\r\n+CSMINS: 0,0\r\n\r\nOK\r\n
uart_packet-1:   43.550 RX: \r\nNORMAL POWER DOWN\r\n
uart_packet-1:   44.173 RX err: \x00
uart_packet-1:   48.429 RX: \r\nRDY\r\n\r\n+CFUN: 1\r\n
uart_packet-1:   49.011 RX: \r\n+CPIN: NOT INSERTED\r\n
uart_packet-1:   52.539 TX: AT+CSMINS?\r
uart_packet-1:   52.541 RX: AT+CSMINS?\r\r\n+CSMINS: 0,0\r\n\r\nOK\r\n
uart_packet-1:   74.417 TX: ATI0\r
uart_packet-1:   74.418 RX: ATI0\r
uart_packet-1:   74.419 RX: \r\nSIM800 R14.18\r\n\r\nOK\r\n
uart_packet-1:   75.563 TX: AT+CCLK="22/07/23,11:54:36+00"\r
uart_packet-1:   75.567 RX: AT+CCLK="22/07/23,11:54:36+00"\r\r\nOK\r\n

@sespivak sespivak force-pushed the uart_packet branch 2 times, most recently from 7834577 to 30853a9 Compare July 26, 2022 17:34
@sespivak sespivak changed the title UART packet decoder uart_packet: decoder for logging and analysis of uart packets of variable length Jul 28, 2022
@sespivak sespivak closed this Jul 31, 2022
@sespivak sespivak reopened this Jul 31, 2022
@sespivak sespivak marked this pull request as draft August 1, 2022 03:32
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sespivak commented Aug 1, 2022

Replaced by PR #90, except logging option print_sec and better ascii format

@sespivak sespivak closed this Aug 1, 2022
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