uart: fixed packet assembly by length

sigrokproject · Jul 31, 2022 · fa388e9 · fa388e9
1 parent 45264f3
commit fa388e9
Showing 1 changed file with 4 additions and 2 deletions.
diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
@@ -228,8 +228,10 @@ def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
         self.bw = (self.options['data_bits'] + 7) // 8
         packet_idle_us = self.options['packet_idle_us']
-        self.packet_idle_samples = int(round(packet_idle_us * 1e-6 * self.samplerate))
-        if not self.packet_idle_samples >= 0:
+        if packet_idle_us > 0:
+            self.packet_idle_samples = int(round(packet_idle_us * 1e-6 * self.samplerate))
+            self.packet_idle_samples = max(1, self.packet_idle_samples)
+        else:
             self.packet_idle_samples = None
 
     def metadata(self, key, value):