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Adding Future Avalanche Board design files #109
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Which branch/commit of fpga-shells were you using? If I do a clean checkout I get this:
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Hi, I was using this version of FPGA_Shell . It hasn't been accepted into the main branch of FPGA_Shell yet. Thanks, |
FYI, @erikdanie has updated and merged the PolarFire code for Vera IOfpga, and it's now stable and running. Please take a look at the new scala code, I'd like to get your PRs for Avalanche updated and tested. What do we need to connect the Avalanche ethernet port up to something we can use in Linux? I'm also quite curious what we can do with the SerDES SFP cage. |
Hi, Thanks, |
Can this be used on the Polarfire Eval Kit ? |
Hi,
Opening pull request to add design files for the Future Avalanche Board.
This design contains an RV64IMAFDC rocket core with SiFive Blocks (UART and GPIO).
The GPIOs are connected to the 4 LEDs on the board and the UART is connected to the FTDI UART pins.
There is also a script in the FPGA shell which I'll put a link to in a comment to follow that will build the complete libero project in Libero 12. all the constraints are also included in the FPGA-Shell. I will create a pull request for this in the next few minutes.
Let me know if you need me to do any updates to this work.
Thanks,
Ciaran