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shili2017/README.md

Hi there πŸ‘‹

  • πŸŽ† Graduate engineer at Arm Austin
  • 🏫 EFZ '17 | SJTU '21 | CMU '23
  • πŸ”­ Interested in computer architecture (don't like reading papers)
  • 🌱 Currently learning digital IC design & verification & skiing (especially skiing)
  • πŸ₯₯ Good at making coconut desserts (zzzzz)
  • πŸ‰ Eat watermelons every summer... (and winter)
  • πŸ’€ Sleep 12 hours every day... (people who don't like me sleep double time every day)
  • πŸ“« How to reach me: [email protected]

Pinned Loading

  1. UMJI-VE450-21SU/Ria UMJI-VE450-21SU/Ria Public

    UM-SJTU JI VE450 2021 Summer Capstone Design Project

    SystemVerilog 10 1

  2. OSCPU-Zhoushan/Zhoushan OSCPU-Zhoushan/Zhoushan Public

    Open Source Chip Project by University (OSCPU) - Zhoushan Core

    Scala 46 13

  3. CONNECT-AXI CONNECT-AXI Public

    Verilog 5

  4. CherrySprings/CherrySprings CherrySprings/CherrySprings Public

    Scala 16 2