Merge pull request #7 from scopeInfinity/verilog

Execution in Verilog

Author: scopeInfinity

Makefile

@@ -2,9 +2,9 @@ SRC_DIR=.
 BUILD_DIR=build
 OUTPUT_DIR=output
 
-.PHONY: clean test all run_ping_pong all_programs_binary all_programs_resolved
+.PHONY: clean test all run_verilog_io run_ping_pong all_programs_binary all_programs_resolved output_rom_binaries
 
-all: all_programs_binary all_programs_resolved
+all: all_programs_binary all_programs_resolved verilog_modules
 
 clean:
 	rm -rf $(BUILD_DIR)
@@ -19,6 +19,8 @@ test: pytest test_verilog_modules
 
 all_programs_binary: $(patsubst programs/%.asm, $(OUTPUT_DIR)/programs/%.bin, $(shell find programs/ -name '*.asm'))
 
+output_rom_binaries: $(OUTPUT_DIR)/programs/boot_sequence.bin $(OUTPUT_DIR)/programs/ping_pong.bin
+
 $(OUTPUT_DIR)/programs/%.bin: programs/%.asm
 	mkdir -p $(dir $@)
 	python3 -m planner asm -b $^ > $@
@@ -31,3 +33,6 @@ $(OUTPUT_DIR)/programs/%_resolved.asm: programs/%.asm
 
 run_ping_pong:
 	python3 -m planner compile_and_execute ping_pong
+
+run_verilog_io:
+	python3 -m planner verilog_io

README.md

@@ -8,12 +8,13 @@ The eventual goal(?) is to build a general-purpose processor integrated with sim
 ## Sample Programs
 
 * Ping Pong
+  * 16x8 LED display with W/S/Up/Down keyboard controller
   * Source: [ping_pong.asm](programs/ping_pong.asm)
   * Generate resolved assembly: `python3 -m planner asm -r programs/ping_pong.asm` [[example](output/programs/ping_pong_resolved.asm)]
   * Generate binary: `python3 -m planner asm -b programs/ping_pong.asm` [[example](output/programs/ping_pong.bin)]
-  * Run on emulator: `python3 -m planner compile_and_execute ping_pong`
-    * 16x8 LED display with W/S/Up/Down keyboard controller
+  * Run on python emulator: `python3 -m planner compile_and_execute ping_pong`
     * ![image](https://github.com/user-attachments/assets/9fa2f68f-73ae-465c-a29c-cc92b0dc421a)
+  * Run on verilog emulator: `make verilog_simulate`
 
 ## Design
 

emulator/Makefile.mk

@@ -1,11 +1,25 @@
 BUILD_EMULATOR = $(BUILD_DIR)/emulator
 SRC_EMULATOR = $(SRC_DIR)/emulator
 
-.PHONY: test_verilog_modules
+.PHONY: verilog_modules test_verilog_modules verilog_data_prerequisites verilog_simulate
 
-$(BUILD_EMULATOR)/%_test: $(SRC_EMULATOR)/%_test.v
+$(BUILD_EMULATOR)/%_test: $(SRC_EMULATOR)/%_test.v $(SRC_EMULATOR)/%.v
 	mkdir -p $(dir $@)
-	iverilog -o $@ $^
+	iverilog -o $@ $<
+
+verilog_modules: $(BUILD_EMULATOR)/executable_chipset $(patsubst $(SRC_EMULATOR)/%_test.v, $(BUILD_EMULATOR)/%_test, $(shell find $(SRC_EMULATOR) -name '*_test.v'))
+	mkdir -p $(BUILD_EMULATOR)/io
+
+verilog_data_prerequisites: output_rom_binaries
 
 test_verilog_modules: $(patsubst $(SRC_EMULATOR)/%_test.v, $(BUILD_EMULATOR)/%_test, $(shell find $(SRC_EMULATOR) -name '*_test.v'))
+	$(MAKE) verilog_data_prerequisites
 	$(foreach test_name, $^, echo "Executing $(test_name)" && ./$(test_name))
+
+$(BUILD_EMULATOR)/executable_chipset: $(SRC_EMULATOR)/executable_chipset.v
+	$(MAKE) verilog_data_prerequisites
+	mkdir -p $(dir $@)
+	iverilog -o $@ $^
+
+verilog_simulate: $(BUILD_EMULATOR)/executable_chipset
+	./$^ | $(MAKE) run_verilog_io