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scopeInfinityscopeInfinity
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Merge pull request #6 from scopeInfinity/rom
Define boot sequence
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‎README.md

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@@ -12,85 +12,28 @@ The eventual goal(?) is to build a general-purpose processor integrated with sim
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* Generate resolved assembly: `python3 -m planner asm -r programs/ping_pong.asm` [[example](output/programs/ping_pong_resolved.asm)]
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* Generate binary: `python3 -m planner asm -b programs/ping_pong.asm` [[example](output/programs/ping_pong.bin)]
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* Run on emulator: `python3 -m planner compile_and_execute ping_pong`
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* 16x8 LED display with W/S/Up/Down keyboard controller
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* ![image](https://github.com/user-attachments/assets/9fa2f68f-73ae-465c-a29c-cc92b0dc421a)
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## Design
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This section is not up-to date.
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2020
### Specs
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* Address Line: 16-bits
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* Memory Address Line: 16-bits (points to a byte)
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* Memory Value Line: 32-bits (4 bytes)
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* Max Memory: 64KB
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### Constants
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* INSZ = 0x20, independent input bytes
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* OUTSZ = 0x20, independent output bytes
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* IPC = 0x0100, intial value of `PC` (or Program Counter).
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### Memory Allocation
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* `RAM[0:INSZ]` is mapped to I/O module input
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* `RAM[INSZ:OUTSZ]` is mapped to I/O module output
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* `RAM[IPC:IPC+x]` is loaded from ROM. So it essentially contains `.text`, `.data`.
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### Sequencing
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* At boot
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* Load `ROM[0:x]` into `RAM[IPC:IPC+x]`
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* TODO: How?
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### Assembly
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* `.bss` must be the last section.
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* Registers don't really exists. `R[0-7]` are mapped to memory location in `.bss` for convenience and some instructions return response.
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### Architecture
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#### I/O
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Hardware interact asynchronously with IOM (I/O Module) which then interact with RAM at program's will. (WE ARE NOT DOING IT)
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* Input devices publish state change in IOM and Output devices read from IOM.
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* Program use `IN <index>` instructions to read from `IOM_in[index]` and write to `RAM[index]`. `IOM_in` won't cache input and it will be read as real-time value. If a input state needs to be cached, it's the input device responsibility.
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* Program use `OUT <index>` instructions to read `RAM[INSZ+index]` and write to `IOM_out[index]`.
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# TODO
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## Processor
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* Address bits: 8
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* Register size: 8
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* Memory size: 2**8 = 256 bytes
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### Idea
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To keep number of component small, we would split a single instruction execution period into 4 cycles.
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* Reset
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* Set `PC = 0`
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* sub-cycle clock to cycle-0
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* Cycle 0
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* Fetch instruction from `ROM[$PC]` into `pin_INS`
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* Cycle 1
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* Perform first read
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## Assembler
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### Details
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* Registers: R0, R1, R2, R3 or `R{NUM}`
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* Input/Output pin: IO0, IO1, ..., IO7 or `IO{NUM}` (8-bits)
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### Instructions
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* `IN R{NUM}`: short-blocking input with 8-bit response.
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* `OUT R{NUM}`: short-blocking 8-bit output.
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## Syntax: High Level
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Not yet defined.
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* Memory layout: [here](planner/memory.py)
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#### Boot Sequence
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* `programs/boot_sequence.asm` binary (aka `BROM`) is mapped from address_line `BOOTSEQUENCE_LOAD = 0x30`
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* Memory Read
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* If `BOOTSEQUENCE_ORG <= address_line < DEFAULT_PROGRAM_ORG`, pulls value from `BROM`
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* Otherwise, pulls the value from `RAM`
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* Execution starts with `PC` at `BOOTSEQUENCE_ORG = 0x34`
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* `BROM` goal is to copy `PROM` to RAM at `DEFAULT_PROGRAM_ORG = 0x80`
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* Followed by `jmp DEFAULT_PROGRAM_ORG`
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#### PROM
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* Programs like `programs/ping_pong.asm` are translated into binary and are referred to as `PROM`.
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* `PROM` is connected to <chipset> as input-output device.
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* The equivalent program is loaded in RAM at `DEFAULT_PROGRAM_ORG = 0x80`, followed by execution after boot sequence.

‎output/programs/3_led_switch.bin

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00000000 00000000 00000000 00001100
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00001100 00000000 00000000 00000000
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00100100 00000010 00000100 00000101
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00000100 00000100 00000110 00000100
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00110101 00001001 01000000 00000000

‎output/programs/boot_sequence.bin

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00000000 00000000 00000000 00111100
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01000000 00000000 00000000 00000000
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00110100 00000010 00000000 00000000
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00000100 00000100 00010000 00000000
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00100100 00000010 00000000 00000000
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00110100 00000010 00010100 00000000
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00110100 00000010 00000100 00000001
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00110100 00000010 00001000 01000000
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00000100 00000100 00010000 00000100
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00100100 00000010 00001100 00100000
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00000100 00000100 00000010 00000000
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00100100 00000010 00000000 00000010
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01110011 00000010 00000000 00000010
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00110100 00000010 00000100 00000100
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00110100 00000010 00001000 10000000
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01110001 00000000 00000000 00000000
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00110101 00001011 01110000 00000000
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00000100 00000100 00000010 00000100
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00100100 00000010 00001100 00000010
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01000100 00000110 00001000 00001100
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01110000 00000010 00001000 00000100
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01110000 00000010 00000100 00000100
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01110001 00000010 00000000 00000100
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01000001 00000000 00000000 00010100
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00110101 00001011 01000000 00000000
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00110101 00001001 10011000 00000000
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01110001 00000010 00000000 00000001
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00110101 00001001 01001100 00000000
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00110101 00001001 10000000 00000000

‎output/programs/boot_sequence_resolved.asm

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PROGRAM_ORG equ 128
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080: MOVC [0], 0
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084: OUT 16, [0]
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088: IN [0], 0
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08c: MOVC [20], 0
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090: MOVC [4], 1
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094: MOVC [8], 64
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098: OUT 16, [4]
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09c: IN [12], 32
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0a0: STORE [[8]], [12]
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0a4: ADDC [8], 4
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0a8: ADDC [4], 4
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0ac: SUBC [0], 4
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0b0: CMP [0], [20]
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0b4: JZ 64, 0
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0b8: JMP 152, 0
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PROGRAM_ORG equ 52
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034: MOVC [0], 0
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038: OUT 2, [0]
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03c: IN [0], 2
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040: SHRC [0], 2
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044: MOVC [4], 4
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048: MOVC [8], 128
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04c: CMPC [0], 0
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050: JZ 112, 0
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054: OUT 2, [4]
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058: IN [12], 2
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05c: STORE [[8]], [12]
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060: ADDC [8], 4
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064: ADDC [4], 4
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068: SUBC [0], 1
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06c: JMP 76, 0
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070: JMP 128, 0

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