Spartan6-Projects

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Table of Content -

A. Indroduction.

B. Projects Description.

1. Single-Dice-Game.
2. UART
3. PWM
4. MIPS-ALU-32bits

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A. Indroduction.

This repository contains projects for Xilinx Spartan 6 FPGA written in VHDL.

They are based on the concepts and techniques learned in following courses :

1. ECD14 : Digital System Design using VHDL/Verilog by Abhay Sharma
2. ECD09 : Computer Architecture and Digital Hardware Design by Prof. D.V. Gadre.

Board used is MINI_SP6-SPARTAN 6 FPGA DEVELOPMENT BOARD bought from
FPGA Tech Solutions, https://fpgatechsolution.com/product/mini-sp6/

How to upload ISE code to the board? Thank you Apoorv Aryan for this demonstration!

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B. Projects Description.

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1. Single-Dice-Game.

This is a simple game based on luck. Player chooses a 3 bit number from 1 to 7 on the DIP Switches 2,3,4 and presses the button. If the random number generated by LFSR Random Number generator (displayed on LD5,LD6,LD7) matches the number that user selected then a green light will indicate a win, otherwise blue light will indicate player has lost the game.

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2. UART

This project implement a UART TX and RX Component working at 9600 baud rate, 8N1. These RX and TX componets are instantiated in the main file and used is following way:

1. The data that FPGA receives on RX_Line is displayed on the 8 USER LEDS. YouTube Video demonstration.
2. To transmit, USER selects 7 bit number from using SW1 DIP switch and K4, K3, K2 Push buttons. Then to transmit the data over TX_line, user presses K1 Push Button.
   YouTube Video demonstration

Feature: The UART RX and TX line can receive and trasmit data simultaneously.

Following images show reveiving of data 'E' (i.e. 0x45 or 0b01000101) over UART and displaying it on 8 USER LEDs and transmitting 'A', 'B', 'C' ... character from FPGA.

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3. PWM

This project generates a PWM signal.
Working: At every positive clock edge, counter counts increases form 0 to 99 and resets to 0 at 100. User can select duticycle using DIP Switches and Push Buttons available on development board. The PWM_out pin remains HIGH for the count in range [0,duticycle) and LOW for count in range [duticycle, 100) and therefore we can achieve 0% to 100% duticycle by this method.

Folowing images shows controlling LED brightness with various duticycles:

0%, 1% and 16% duticycles respectively.

and 32%, 64% and 100% duticycles respectively:

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4. MIPS-ALU-32bits

Designing and simulation of a 32 bit MIPS-ALU. This ALU has functions of all basic ALUs in addition to MIPs features. These are AND, OR, SUM, SUBTRACT, SLT (Set Less Than), NOR and Zero flag.

Concept of this ALU is based on book Computer Architecture and Design by Patterson and Hennessy.
32 bit MIPs ALU uses 32 1 bit MIPS ALU.
Instead of using standard library function on 32 bit operands for above mentioned functions (what book showed in an example), here in this project, I have first made a 1 bit ALU using simple AND gate, NOT gate, OR gate, Full adder, Multiplexer and then this was used as a building block for 32 bit ALU.

Few of simulated results: SLT Operation on 32 bit -

SUBTRACTION on 32 bit -

ADDITION Operation on 32 bit -

More simulated results can seen in the Project specific README.md

(Zero flag feature has to added.)