Fix: #1464 for rv64 zb

rust-lang · Sep 22, 2023 · 51f2b1e · 51f2b1e
1 parent 839c9ec
commit 51f2b1e
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Showing 2 changed files with 5 additions and 9 deletions.
diff --git a/crates/core_arch/src/riscv_shared/zb.rs b/crates/core_arch/src/riscv_shared/zb.rs
@@ -47,8 +47,7 @@ extern "unadjusted" {
 ///
 /// This function is safe to use if the `zbb` target feature is present.
 #[target_feature(enable = "zbb")]
-// See #1464
-// #[cfg_attr(test, assert_instr(orc.b))]
+#[cfg_attr(test, assert_instr(orc.b))]
 #[inline]
 pub unsafe fn orc_b(rs: usize) -> usize {
     #[cfg(target_arch = "riscv32")]
@@ -76,8 +75,7 @@ pub unsafe fn orc_b(rs: usize) -> usize {
 ///
 /// This function is safe to use if the `zbc` target feature is present.
 #[target_feature(enable = "zbc")]
-// See #1464
-// #[cfg_attr(test, assert_instr(clmul))]
+#[cfg_attr(test, assert_instr(clmul))]
 #[inline]
 pub unsafe fn clmul(rs1: usize, rs2: usize) -> usize {
     #[cfg(target_arch = "riscv32")]
@@ -105,8 +103,7 @@ pub unsafe fn clmul(rs1: usize, rs2: usize) -> usize {
 ///
 /// This function is safe to use if the `zbc` target feature is present.
 #[target_feature(enable = "zbc")]
-// See #1464
-// #[cfg_attr(test, assert_instr(clmulh))]
+#[cfg_attr(test, assert_instr(clmulh))]
 #[inline]
 pub unsafe fn clmulh(rs1: usize, rs2: usize) -> usize {
     #[cfg(target_arch = "riscv32")]
@@ -134,8 +131,7 @@ pub unsafe fn clmulh(rs1: usize, rs2: usize) -> usize {
 ///
 /// This function is safe to use if the `zbc` target feature is present.
 #[target_feature(enable = "zbc")]
-// See #1464
-// #[cfg_attr(test, assert_instr(clmulr))]
+#[cfg_attr(test, assert_instr(clmulr))]
 #[inline]
 pub unsafe fn clmulr(rs1: usize, rs2: usize) -> usize {
     #[cfg(target_arch = "riscv32")]

diff --git a/crates/stdarch-test/src/disassembly.rs b/crates/stdarch-test/src/disassembly.rs
@@ -82,7 +82,7 @@ pub(crate) fn disassemble_myself() -> HashSet<Function> {
         // Target features need to be enabled for LLVM objdump on Macos ARM64
         vec!["--mattr=+v8.6a,+crypto,+tme"]
     } else if cfg!(target_arch = "riscv64") {
-        vec!["--mattr=+zk,+zks"]
+        vec!["--mattr=+zk,+zks,+zbc,+zbb"]
     } else {
         vec![]
     };