Update Verilog Code

VerilogCode.v

@@ -0,0 +1,58 @@
+module Square_Rooter(input clk, input[7:0] num, output[15:0] res, output[7:0] buffer_out);
+reg[15:0] res;
+reg[7:0] buffer_out;
+reg[15:0] val;
+reg[7:0] bitIndex;
+reg[7:0] i; 
+reg[7:0] buffer;
+
+always @(posedge clk) begin
+	res = 0;
+	bitIndex = 14;
+	i = 0;
+	buffer = 4;
+	val = num << 8;
+
+	while(!((((val >>> 15) & 1) | ((val >>> 14) & 1)) == 1)) begin
+		val = val << 2;
+		buffer = buffer + 1;
+	end
+
+	while(i < 8)begin
+		if(!(val < res + ( 1 << bitIndex))) begin
+			val = (val + ~(res+(1<<bitIndex))+1);
+			res = res + (1 << (bitIndex + 1));
+		end
+		res = res >>> 1;
+		bitIndex = (bitIndex + ~2 + 1);
+		i = i + 1;
+	end
+
+	buffer_out = buffer;
+end
+
+endmodule
+
+module Test_Bench;
+	reg[7:0] i;
+	reg clk;
+	reg [7:0]num = 0;
+	wire[15:0] res;
+	wire[7:0] buffer_out;
+
+	Square_Rooter sqrt(clk,num,res, buffer_out);
+
+	initial begin
+		forever begin
+			#5 clk = 0; num = num+1;
+			#5 clk = 1;
+			#5 $display("Square Root of %d with a buffer of %d:\n%b\n",num,buffer_out,res);
+		end	
+	end
+
+	//This program will run from num = 1 to num = 255
+	initial begin
+		#3825
+		$finish;
+	end
+endmodule

a.out

@@ -0,0 +1,168 @@
+#! /ivl-install/bin/vvp
+:ivl_version "11.0 (devel)" "(s20150603-565-g3f24557e)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "vhdl_textio";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0000000003c17c30 .scope module, "Test_Bench" "Test_Bench" 2 36;
+ .timescale 0 0;
+v0000000003c08170_0 .net "buffer_out", 7 0, v0000000003c07db0_0;  1 drivers
+v0000000003d3cc20_0 .var "clk", 0 0;
+v0000000003d3ccc0_0 .var "num", 7 0;
+v0000000003d3cd60_0 .net "res", 15 0, v0000000003c08030_0;  1 drivers
+S_0000000003c17dc0 .scope module, "sqrt" "Square_Rooter" 2 43, 2 1 0, S_0000000003c17c30;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 8 "num";
+    .port_info 2 /OUTPUT 16 "res";
+    .port_info 3 /OUTPUT 8 "buffer_out";
+v0000000003c17f50_0 .var "bitIndex", 7 0;
+v0000000003c07d10_0 .var "buffer", 7 0;
+v0000000003c07db0_0 .var "buffer_out", 7 0;
+v0000000003c07e50_0 .net "clk", 0 0, v0000000003d3cc20_0;  1 drivers
+v0000000003c07ef0_0 .var "i", 7 0;
+v0000000003c07f90_0 .net "num", 7 0, v0000000003d3ccc0_0;  1 drivers
+v0000000003c08030_0 .var "res", 15 0;
+v0000000003c080d0_0 .var "val", 15 0;
+E_0000000003c06240 .event posedge, v0000000003c07e50_0;
+    .scope S_0000000003c17dc0;
+T_0 ;
+    %wait E_0000000003c06240;
+    %pushi/vec4 0, 0, 16;
+    %store/vec4 v0000000003c08030_0, 0, 16;
+    %pushi/vec4 14, 0, 8;
+    %store/vec4 v0000000003c17f50_0, 0, 8;
+    %pushi/vec4 0, 0, 8;
+    %store/vec4 v0000000003c07ef0_0, 0, 8;
+    %pushi/vec4 4, 0, 8;
+    %store/vec4 v0000000003c07d10_0, 0, 8;
+    %load/vec4 v0000000003c07f90_0;
+    %pad/u 16;
+    %ix/load 4, 8, 0;
+    %flag_set/imm 4, 0;
+    %shiftl 4;
+    %store/vec4 v0000000003c080d0_0, 0, 16;
+T_0.0 ;
+    %load/vec4 v0000000003c080d0_0;
+    %pad/u 32;
+    %ix/load 4, 15, 0;
+    %flag_set/imm 4, 0;
+    %shiftr 4;
+    %pushi/vec4 1, 0, 32;
+    %and;
+    %load/vec4 v0000000003c080d0_0;
+    %pad/u 32;
+    %ix/load 4, 14, 0;
+    %flag_set/imm 4, 0;
+    %shiftr 4;
+    %pushi/vec4 1, 0, 32;
+    %and;
+    %or;
+    %pushi/vec4 1, 0, 32;
+    %cmp/e;
+    %flag_get/vec4 4;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz T_0.1, 8;
+    %load/vec4 v0000000003c080d0_0;
+    %ix/load 4, 2, 0;
+    %flag_set/imm 4, 0;
+    %shiftl 4;
+    %store/vec4 v0000000003c080d0_0, 0, 16;
+    %load/vec4 v0000000003c07d10_0;
+    %addi 1, 0, 8;
+    %store/vec4 v0000000003c07d10_0, 0, 8;
+    %jmp T_0.0;
+T_0.1 ;
+T_0.2 ;
+    %load/vec4 v0000000003c07ef0_0;
+    %pad/u 32;
+    %cmpi/u 8, 0, 32;
+    %jmp/0xz T_0.3, 5;
+    %load/vec4 v0000000003c080d0_0;
+    %pad/u 32;
+    %load/vec4 v0000000003c08030_0;
+    %pad/u 32;
+    %pushi/vec4 1, 0, 32;
+    %ix/getv 4, v0000000003c17f50_0;
+    %shiftl 4;
+    %add;
+    %cmp/u;
+    %flag_get/vec4 5;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.4, 8;
+    %load/vec4 v0000000003c080d0_0;
+    %load/vec4 v0000000003c08030_0;
+    %pushi/vec4 1, 0, 16;
+    %ix/getv 4, v0000000003c17f50_0;
+    %shiftl 4;
+    %add;
+    %inv;
+    %add;
+    %addi 1, 0, 16;
+    %store/vec4 v0000000003c080d0_0, 0, 16;
+    %load/vec4 v0000000003c08030_0;
+    %pushi/vec4 1, 0, 16;
+    %load/vec4 v0000000003c17f50_0;
+    %pad/u 32;
+    %addi 1, 0, 32;
+    %ix/vec4 4;
+    %shiftl 4;
+    %add;
+    %store/vec4 v0000000003c08030_0, 0, 16;
+T_0.4 ;
+    %load/vec4 v0000000003c08030_0;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %shiftr 4;
+    %store/vec4 v0000000003c08030_0, 0, 16;
+    %load/vec4 v0000000003c17f50_0;
+    %addi 254, 0, 8;
+    %store/vec4 v0000000003c17f50_0, 0, 8;
+    %load/vec4 v0000000003c07ef0_0;
+    %addi 1, 0, 8;
+    %store/vec4 v0000000003c07ef0_0, 0, 8;
+    %jmp T_0.2;
+T_0.3 ;
+    %load/vec4 v0000000003c07d10_0;
+    %store/vec4 v0000000003c07db0_0, 0, 8;
+    %jmp T_0;
+    .thread T_0;
+    .scope S_0000000003c17c30;
+T_1 ;
+    %pushi/vec4 0, 0, 8;
+    %store/vec4 v0000000003d3ccc0_0, 0, 8;
+    %end;
+    .thread T_1;
+    .scope S_0000000003c17c30;
+T_2 ;
+T_2.0 ;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0000000003d3cc20_0, 0, 1;
+    %load/vec4 v0000000003d3ccc0_0;
+    %addi 1, 0, 8;
+    %store/vec4 v0000000003d3ccc0_0, 0, 8;
+    %delay 5, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0000000003d3cc20_0, 0, 1;
+    %delay 5, 0;
+    %vpi_call 2 49 "$display", "Square Root of %d with a buffer of %d:\012%b\012", v0000000003d3ccc0_0, v0000000003c08170_0, v0000000003d3cd60_0 {0 0 0};
+    %jmp T_2.0;
+    %end;
+    .thread T_2;
+    .scope S_0000000003c17c30;
+T_3 ;
+    %delay 3825, 0;
+    %vpi_call 2 56 "$finish" {0 0 0};
+    %end;
+    .thread T_3;
+# The file index is used to find the file name in the following table.
+:file_names 3;
+    "N/A";
+    "<interactive>";
+    "VerilogCode.v";